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https://github.com/FEX-Emu/FEX.git
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Ryan Houdek
0c7c7ba670
Most of these were relying on the upper 16bits of the 80bit MM registers to be zero. This isn't necessarily true as one will find out when running this under the host runner.
64 lines
998 B
NASM
64 lines
998 B
NASM
%ifdef CONFIG
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{
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"RegData": {
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"MM0": "0x20A121A222A323A4",
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"MM1": "0x0041004300450047",
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"MM2": "0x0",
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"MM3": "0x0",
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"MM4": "0x0"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x1
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mov [rdx + 8 * 2], rax
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mov rax, 0x0
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mov [rdx + 8 * 3], rax
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mov rax, 0x8
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mov [rdx + 8 * 4], rax
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mov rax, 0x0
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mov [rdx + 8 * 5], rax
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; Will Zero
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mov rax, 0x10
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mov [rdx + 8 * 6], rax
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mov rax, 0x0
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mov [rdx + 8 * 7], rax
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; Will Zero
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mov rax, 0x20
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mov [rdx + 8 * 8], rax
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mov rax, 0x0
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mov [rdx + 8 * 9], rax
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; Will Zero
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mov rax, 0x40
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mov [rdx + 8 * 10], rax
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mov rax, 0x0
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mov [rdx + 8 * 11], rax
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movq mm0, [rdx + 8 * 0]
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movq mm1, [rdx + 8 * 0]
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movq mm2, [rdx + 8 * 0]
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movq mm3, [rdx + 8 * 0]
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movq mm4, [rdx + 8 * 0]
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psrlw mm0, [rdx + 8 * 2]
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psrlw mm1, [rdx + 8 * 4]
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psrlw mm2, [rdx + 8 * 6]
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psrlw mm3, [rdx + 8 * 8]
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psrlw mm4, [rdx + 8 * 10]
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hlt
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