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https://github.com/FEX-Emu/FEX.git
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Ryan Houdek
0c7c7ba670
Most of these were relying on the upper 16bits of the 80bit MM registers to be zero. This isn't necessarily true as one will find out when running this under the host runner.
49 lines
927 B
NASM
49 lines
927 B
NASM
%ifdef CONFIG
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{
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"RegData": {
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"MM0": "0x4142434445467778",
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"MM1": "0x4142434477784748",
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"MM2": "0x4142777845464748",
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"MM3": "0x7778434445464748",
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"MM4": "0x4142434445467778",
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"MM5": "0x4142434477784748",
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"MM6": "0x4142777845464748",
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"MM7": "0x7778434445464748"
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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mov rax, 0x7172737475767778
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mov [rdx + 8 * 2], rax
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movq mm0, [rdx + 8 * 0]
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movq mm1, [rdx + 8 * 0]
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movq mm2, [rdx + 8 * 0]
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movq mm3, [rdx + 8 * 0]
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movq mm4, [rdx + 8 * 0]
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movq mm5, [rdx + 8 * 0]
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movq mm6, [rdx + 8 * 0]
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movq mm7, [rdx + 8 * 0]
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pinsrw mm0, eax, 0
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pinsrw mm1, eax, 1
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pinsrw mm2, eax, 2
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pinsrw mm3, eax, 3
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pinsrw mm4, [rdx + 8 * 2], 0
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pinsrw mm5, [rdx + 8 * 2], 1
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pinsrw mm6, [rdx + 8 * 2], 2
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pinsrw mm7, [rdx + 8 * 2], 3
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hlt
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