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https://github.com/FEX-Emu/FEX.git
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Ryan Houdek
1ce27a5e6b
In quite a few locations we are mixing the case that SVE256 == AVX or that AVX means the guest register size is 256-bit. While this is true today, this is entanglement is going to change very quickly and cause confusion in follow-up PRs. Now we have SVE128, SVE256, and SVE2 HostFeatures to disambiguate the different features which mean different things. This PR keeps the alias that `SupportsAVX` = `SupportsSVE256 && SupportsSVE2` but that alias is going to very quickly change its definition.
34 lines
990 B
C++
34 lines
990 B
C++
// SPDX-License-Identifier: MIT
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#pragma once
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#include <FEXCore/fextl/memory.h>
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namespace FEXCore {
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class CPUIDEmu;
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}
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namespace FEXCore::Utils {
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class IntrusivePooledAllocator;
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}
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namespace FEXCore::IR {
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class Pass;
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class RegisterAllocationPass;
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class RegisterAllocationData;
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fextl::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool SupportsTSOImm9, const FEXCore::CPUIDEmu* CPUID);
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fextl::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination(bool SupportsSVE256);
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fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadFlagCalculationEliminination();
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fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination();
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fextl::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass();
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namespace Validation {
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fextl::unique_ptr<FEXCore::IR::Pass> CreateIRValidation();
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fextl::unique_ptr<FEXCore::IR::Pass> CreateRAValidation();
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} // namespace Validation
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namespace Debug {
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fextl::unique_ptr<FEXCore::IR::Pass> CreateIRDumper();
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}
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} // namespace FEXCore::IR
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