mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 17:00:19 +02:00
Paulo Matos
3d92c1fb32
Fix SoftFloat IsNan - custom detection matches IEEE754 semantics. Sets Invalid Operation flags properly for NaN comparisons. Fixes: GCC-C-execute-ieee-fp-cmp-8l test __builtin_isunordered() now returns correct values for both NaN and normal operands
658 lines
17 KiB
C++
658 lines
17 KiB
C++
// SPDX-License-Identifier: MIT
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#pragma once
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/fextl/sstream.h>
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#include <FEXCore/fextl/string.h>
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#include <FEXHeaderUtils/BitUtils.h>
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#include "cephes_128bit.h"
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#include <cmath>
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#include <cstring>
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#include <stdint.h>
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#include "Common/VectorRegType.h"
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extern "C" {
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#include "SoftFloat-3e/platform.h"
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#include "SoftFloat-3e/softfloat.h"
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}
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struct FEX_PACKED X80SoftFloat {
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#ifdef _M_X86_64
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// Define this to push some operations to x87
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// Only useful to see if precision loss is killing something
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// #define DEBUG_X86_FLOAT
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#ifdef DEBUG_X86_FLOAT
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#define BIGFLOAT long double
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#define BIGFLOATSIZE 10
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#else
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#define BIGFLOAT float128_t
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#define BIGFLOATSIZE 16
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#endif
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#elif defined(_M_ARM_64)
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#define BIGFLOAT float128_t
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#define BIGFLOATSIZE 16
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#else
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#error No 128bit float for this target!
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#endif
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uint64_t Significand : 64;
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uint16_t Exponent : 15;
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uint16_t Sign : 1;
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X80SoftFloat() {
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memset(this, 0, sizeof(*this));
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}
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X80SoftFloat(uint16_t _Sign, uint16_t _Exponent, uint64_t _Significand)
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: Significand {_Significand}
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, Exponent {_Exponent}
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, Sign {_Sign} {}
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fextl::string str() const {
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fextl::ostringstream string;
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string << std::hex << Sign;
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string << "_" << Exponent;
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string << "_" << (Significand >> 63);
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string << "_" << (Significand & ((1ULL << 63) - 1));
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return string.str();
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}
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// Ops
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FADD(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[rhs]; # st1
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fldt %[lhs]; # st0
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faddp;
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs), [rhs] "m"(rhs)
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: "st", "st(1)");
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return Result;
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#else
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return extF80_add(state, lhs, rhs);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSUB(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[rhs]; # st1
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fldt %[lhs]; # st0
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fsubp;
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs), [rhs] "m"(rhs)
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: "st", "st(1)");
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return Result;
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#else
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return extF80_sub(state, lhs, rhs);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FMUL(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[rhs]; # st1
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fldt %[lhs]; # st0
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fmulp;
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs), [rhs] "m"(rhs)
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: "st", "st(1)");
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return Result;
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#else
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return extF80_mul(state, lhs, rhs);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FDIV(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[rhs]; # st1
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fldt %[lhs]; # st0
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fdivp;
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs), [rhs] "m"(rhs)
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: "st", "st(1)");
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return Result;
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#else
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return extF80_div(state, lhs, rhs);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
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#if defined(DEBUG_X86_FLOAT)
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[rhs]; # st1
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fldt %[lhs]; # st0
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fprem;
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fstpt %[result];
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ffreep %%st(0);
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs), [rhs] "m"(rhs)
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: "st", "st(1)");
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return Result;
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#else
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/*
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* Check for invalid operation cases first - Intel FPREM sets Invalid Operation
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* for several cases including infinity dividend and zero divisor.
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*/
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X80SoftFloat result = 0;
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if (HandleInfinityOp(state, lhs, result)) {
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return result;
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} else if (lhs.Exponent == 0x7FFF && (lhs.Significand & 0x7FFFFFFFFFFFFFFFULL)) { // NaN
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// propagate NaN
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state->exceptionFlags |= softfloat_flag_invalid;
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return lhs;
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}
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// Check for zero divisor - fprem(x, 0) is invalid operation
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if (rhs.Exponent == 0 && rhs.Significand == 0) {
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state->exceptionFlags |= softfloat_flag_invalid;
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// Return QNaN
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result.Sign = 0;
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result.Exponent = 0x7FFF;
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result.Significand = 0xC000000000000000ULL;
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return result;
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}
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/*
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* FPREM is not an IEEE-754 remainder. From the Intel spec:
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*
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* Computes the remainder obtained from dividing the value in the ST(0)
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* register (the dividend) by the value in the ST(1) register (the divisor
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* or modulus), and stores the result in ST(0). The remainder represents the
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* following value:
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*
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* Remainder := ST(0) − (Q * ST(1))
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*
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* Here, Q is an integer value that is obtained by truncating the
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* floating-point number quotient of [ST(0) / ST(1)] toward zero.
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*
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* We implement this sequence literally. softfloat_round_minMag means
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* "truncate towards zero".
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*/
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extFloat80_t quotient = extF80_div(state, lhs, rhs);
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extFloat80_t Q = extF80_roundToInt(state, quotient, softfloat_round_minMag, true);
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bool Q_zero = Q.signif == 0 && (Q.signExp & ~(1 << 15)) == 0;
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if (Q_zero) {
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return lhs;
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} else {
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return extF80_sub(state, lhs, extF80_mul(state, Q, rhs));
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}
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM1(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
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#if defined(DEBUG_X86_FLOAT)
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[rhs]; # st1
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fldt %[lhs]; # st0
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fprem1;
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fstpt %[result];
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ffreep %%st(0);
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs), [rhs] "m"(rhs)
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: "st", "st(1)");
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return Result;
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#else
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return extF80_rem(state, lhs, rhs);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(softfloat_state* state, const X80SoftFloat& lhs) {
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return extF80_roundToInt(state, lhs, state->roundingMode, false);
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(softfloat_state* state, const X80SoftFloat& lhs, uint_fast8_t RoundMode) {
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return extF80_roundToInt(state, lhs, RoundMode, false);
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FXTRACT_SIG(const X80SoftFloat& lhs) {
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#if defined(DEBUG_X86_FLOAT)
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[lhs]; # st0
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fxtract;
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fstpt %[result];
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ffreep %%st(0);
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs)
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: "st", "st(1)");
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return Result;
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#else
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// Zero is a special case, the significand for +/- 0 is +/- zero.
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if (lhs.Exponent == 0x0 && lhs.Significand == 0x0) {
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return lhs;
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}
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X80SoftFloat Tmp = lhs;
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Tmp.Exponent = 0x3FFF;
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Tmp.Sign = lhs.Sign;
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return Tmp;
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FXTRACT_EXP(const X80SoftFloat& lhs) {
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#if defined(DEBUG_X86_FLOAT)
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[lhs]; # st0
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fxtract;
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ffreep %%st(0);
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs)
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: "st", "st(1)");
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return Result;
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#else
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// Zero is a special case, the exponent is always -inf
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if (lhs.Exponent == 0x0 && lhs.Significand == 0x0) {
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X80SoftFloat Result(1, 0x7FFFUL, 0x8000'0000'0000'0000UL);
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return Result;
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}
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int32_t TrueExp = lhs.Exponent - ExponentBias;
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return i32_to_extF80(TrueExp);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static void
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FCMP(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs, bool* eq, bool* lt, bool* nan) {
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*eq = extF80_eq(state, lhs, rhs);
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*lt = extF80_lt(state, lhs, rhs);
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// Use IEEE 754 semantics: unordered if neither <, =, nor > is true
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// This is more reliable than custom NaN detection
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bool gt = !(*eq) && !(*lt) && extF80_le(state, rhs, lhs);
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*nan = !(*eq) && !(*lt) && !gt;
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSCALE(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[rhs]; # st1
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fldt %[lhs]; # st0
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fscale; # st0 = st0 * 2^(rdint(st1))
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fstpt %[result];
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ffreep %%st(0);
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs), [rhs] "m"(rhs)
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: "st", "st(1)");
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return Result;
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#else
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extFloat80_t Zero {0, 0};
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if (extF80_eq(state, lhs, Zero)) {
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return lhs;
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}
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X80SoftFloat Int = FRNDINT(state, rhs, softfloat_round_minMag);
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BIGFLOAT Src2_d = Int.ToFMax(state);
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Src2_d = FEXCore::cephes_128bit::exp2l(Src2_d);
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X80SoftFloat Src2_X80(state, Src2_d);
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X80SoftFloat Result = extF80_mul(state, lhs, Src2_X80);
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return Result;
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat F2XM1(softfloat_state* state, const X80SoftFloat& lhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[lhs]; # st0
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f2xm1; # st0 = 2^st(0) - 1
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs)
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: "st");
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return Result;
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#else
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auto Src1_d = lhs.ToFMax(state);
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auto Result = FEXCore::cephes_128bit::exp2l(Src1_d);
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static const float128_t one {0x0ULL, 0x3fff000000000000ULL};
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return X80SoftFloat(state, f128_sub(state, Result, one));
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FYL2X(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[rhs]; # st(1)
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fldt %[lhs]; # st(0)
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fyl2x; # st(1) * log2l(st(0))
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs), [rhs] "m"(rhs)
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: "st", "st(1)");
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return Result;
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#else
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auto Src1_d = lhs.ToFMax(state);
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auto Src2_d = rhs.ToFMax(state);
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auto Tmp = f128_mul(state, Src2_d, FEXCore::cephes_128bit::log2l(Src1_d));
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return X80SoftFloat(state, Tmp);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FATAN(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[lhs];
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fldt %[rhs];
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fpatan;
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs), [rhs] "m"(rhs)
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: "st", "st(1)");
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return Result;
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#else
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BIGFLOAT Src1_d = lhs.ToFMax(state);
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BIGFLOAT Src2_d = rhs.ToFMax(state);
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BIGFLOAT Tmp = FEXCore::cephes_128bit::atan2l(Src1_d, Src2_d);
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return X80SoftFloat(state, Tmp);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FTAN(softfloat_state* state, const X80SoftFloat& lhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[lhs]; # st0
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fptan;
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ffreep %%st(0);
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs)
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: "st");
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return Result;
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#else
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X80SoftFloat result;
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if (HandleInfinityOp(state, lhs, result)) {
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return result;
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}
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BIGFLOAT Src_d = lhs.ToFMax(state);
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Src_d = FEXCore::cephes_128bit::tanl(Src_d);
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return X80SoftFloat(state, Src_d);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSIN(softfloat_state* state, const X80SoftFloat& lhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[lhs]; # st0
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fsin;
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs)
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: "st");
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return Result;
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#else
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X80SoftFloat result;
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if (HandleInfinityOp(state, lhs, result)) {
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return result;
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}
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BIGFLOAT Src_d = lhs.ToFMax(state);
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Src_d = FEXCore::cephes_128bit::sinl(Src_d);
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return X80SoftFloat(state, Src_d);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FCOS(softfloat_state* state, const X80SoftFloat& lhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[lhs]; # st0
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fcos;
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fstpt %[result];
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)"
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: [result] "=m"(Result)
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: [lhs] "m"(lhs)
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: "st");
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return Result;
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#else
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X80SoftFloat result;
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if (HandleInfinityOp(state, lhs, result)) {
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return result;
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}
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BIGFLOAT Src_d = lhs.ToFMax(state);
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Src_d = FEXCore::cephes_128bit::cosl(Src_d);
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return X80SoftFloat(state, Src_d);
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#endif
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}
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FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSQRT(softfloat_state* state, const X80SoftFloat& lhs) {
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#ifdef DEBUG_X86_FLOAT
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BIGFLOAT Result;
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asm(R"(
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fninit;
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fldt %[lhs]; # st0
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fsqrt;
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fstpt %[result];
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)"
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: [result] "=m"(Result)
|
||
: [lhs] "m"(lhs)
|
||
: "st");
|
||
|
||
return Result;
|
||
#else
|
||
return extF80_sqrt(state, lhs);
|
||
#endif
|
||
}
|
||
|
||
float ToF32(softfloat_state* state) const {
|
||
const float32_t Result = extF80_to_f32(state, *this);
|
||
return FEXCore::BitCast<float>(Result);
|
||
}
|
||
|
||
double ToF64(softfloat_state* state) const {
|
||
const float64_t Result = extF80_to_f64(state, *this);
|
||
return FEXCore::BitCast<double>(Result);
|
||
}
|
||
|
||
FEXCore::VectorRegType ToVector() const {
|
||
FEXCore::VectorRegType Ret {};
|
||
memcpy(&Ret, this, sizeof(*this));
|
||
return Ret;
|
||
}
|
||
|
||
BIGFLOAT ToFMax(softfloat_state* state) const {
|
||
#if BIGFLOATSIZE == 16
|
||
const float128_t Result = extF80_to_f128(state, *this);
|
||
return FEXCore::BitCast<BIGFLOAT>(Result);
|
||
#else
|
||
BIGFLOAT result {};
|
||
memcpy(&result, this, sizeof(result));
|
||
return result;
|
||
#endif
|
||
}
|
||
|
||
int16_t ToI16(softfloat_state* state) const {
|
||
auto rv = extF80_to_i32(state, *this, state->roundingMode, false);
|
||
if (rv > INT16_MAX || rv < INT16_MIN) {
|
||
///< Indefinite value for 16-bit conversions.
|
||
return INT16_MIN;
|
||
} else {
|
||
return rv;
|
||
}
|
||
}
|
||
|
||
int32_t ToI32(softfloat_state* state) const {
|
||
return extF80_to_i32(state, *this, state->roundingMode, false);
|
||
}
|
||
|
||
int64_t ToI64(softfloat_state* state) const {
|
||
return extF80_to_i64(state, *this, state->roundingMode, false);
|
||
}
|
||
|
||
uint64_t ToUI64(softfloat_state* state) const {
|
||
return extF80_to_ui64(state, *this, state->roundingMode, false);
|
||
}
|
||
|
||
void operator=(const int16_t rhs) {
|
||
*this = i32_to_extF80(rhs);
|
||
}
|
||
|
||
void operator=(const int32_t rhs) {
|
||
*this = i32_to_extF80(rhs);
|
||
}
|
||
|
||
void operator=(const uint64_t rhs) {
|
||
*this = ui64_to_extF80(rhs);
|
||
}
|
||
|
||
#if BIGFLOATSIZE == 10
|
||
void operator=(const long double rhs) {
|
||
memcpy(this, &rhs, sizeof(rhs));
|
||
}
|
||
#endif
|
||
|
||
operator void*() {
|
||
return reinterpret_cast<void*>(this);
|
||
}
|
||
|
||
X80SoftFloat(extFloat80_t rhs) {
|
||
Significand = rhs.signif;
|
||
Exponent = rhs.signExp & 0x7FFF;
|
||
Sign = rhs.signExp >> 15;
|
||
}
|
||
|
||
X80SoftFloat(softfloat_state* state, const float rhs) {
|
||
*this = f32_to_extF80(state, FEXCore::BitCast<float32_t>(rhs));
|
||
}
|
||
|
||
X80SoftFloat(softfloat_state* state, const double rhs) {
|
||
*this = f64_to_extF80(state, FEXCore::BitCast<float64_t>(rhs));
|
||
}
|
||
|
||
X80SoftFloat(softfloat_state* state, BIGFLOAT rhs) {
|
||
#if BIGFLOATSIZE == 16
|
||
*this = f128_to_extF80(state, FEXCore::BitCast<float128_t>(rhs));
|
||
#else
|
||
*this = FEXCore::BitCast<long double>(rhs);
|
||
#endif
|
||
}
|
||
|
||
X80SoftFloat(const int16_t rhs) {
|
||
*this = i32_to_extF80(rhs);
|
||
}
|
||
|
||
X80SoftFloat(const int32_t rhs) {
|
||
*this = i32_to_extF80(rhs);
|
||
}
|
||
|
||
X80SoftFloat(const FEXCore::VectorRegType rhs) {
|
||
memcpy(this, &rhs, sizeof(*this));
|
||
}
|
||
|
||
void operator=(extFloat80_t rhs) {
|
||
Significand = rhs.signif;
|
||
Exponent = rhs.signExp & 0x7FFF;
|
||
Sign = rhs.signExp >> 15;
|
||
}
|
||
|
||
operator FEXCore::VectorRegType() const {
|
||
return ToVector();
|
||
}
|
||
|
||
operator extFloat80_t() const {
|
||
extFloat80_t Result {};
|
||
Result.signif = Significand;
|
||
Result.signExp = Exponent | (Sign << 15);
|
||
return Result;
|
||
}
|
||
|
||
static bool IsNan(const X80SoftFloat& lhs) {
|
||
return (lhs.Exponent == 0x7FFF) && (lhs.Significand & IntegerBit) && (lhs.Significand & Bottom62Significand);
|
||
}
|
||
|
||
static bool SignBit(const X80SoftFloat& lhs) {
|
||
return lhs.Sign;
|
||
}
|
||
|
||
private:
|
||
static constexpr uint64_t IntegerBit = (1ULL << 63);
|
||
static constexpr uint64_t Bottom62Significand = ((1ULL << 62) - 1);
|
||
static constexpr uint32_t ExponentBias = 16383;
|
||
|
||
// Helper function to check for infinity and set invalid operation flag.
|
||
// Returns true if infinity is dealt with, false otherwise.
|
||
FEXCORE_PRESERVE_ALL_ATTR static bool HandleInfinityOp(softfloat_state* state, const X80SoftFloat& arg, X80SoftFloat& result) {
|
||
if (arg.Exponent == 0x7FFF && arg.Significand == 0x8000000000000000ULL) {
|
||
state->exceptionFlags |= softfloat_flag_invalid;
|
||
// Return QNaN.
|
||
result.Sign = 0;
|
||
result.Exponent = 0x7FFF;
|
||
result.Significand = 0xC000000000000000ULL;
|
||
return true;
|
||
}
|
||
return false;
|
||
}
|
||
};
|
||
|
||
#ifndef _WIN32
|
||
static_assert(sizeof(X80SoftFloat) == 10, "tword must be 10bytes in size");
|
||
#else
|
||
// Padding on this extends to 16-bytes rather than 10-bytes on WIN32.
|
||
static_assert(sizeof(X80SoftFloat) == 16, "tword must be 16bytes in size");
|
||
#endif
|