mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-07 13:00:15 +02:00
Paulo Matos
2b4ec88dae
This follows discussions from #3413. Followup commits add clang-format file, script and blame ignore lists.
107 lines
3.1 KiB
C++
107 lines
3.1 KiB
C++
// SPDX-License-Identifier: MIT
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/*
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$info$
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tags: ir|opts
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desc: Sanity Checking
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$end_info$
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*/
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#include "Interface/IR/IR.h"
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#include "Interface/IR/IREmitter.h"
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#include "Interface/IR/PassManager.h"
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/Utils/Profiler.h>
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#include <FEXCore/fextl/set.h>
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#include <FEXCore/fextl/sstream.h>
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#include <FEXCore/fextl/unordered_map.h>
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#include <FEXCore/fextl/vector.h>
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#include <functional>
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#include <memory>
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#include <stdint.h>
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#include <utility>
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namespace FEXCore::IR::Validation {
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class ValueDominanceValidation final : public FEXCore::IR::Pass {
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public:
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bool Run(IREmitter* IREmit) override;
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};
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bool ValueDominanceValidation::Run(IREmitter* IREmit) {
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FEXCORE_PROFILE_SCOPED("PassManager::ValueDominanceValidation");
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bool HadError = false;
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auto CurrentIR = IREmit->ViewIR();
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fextl::ostringstream Errors;
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for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
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auto BlockIROp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
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for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) {
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const auto CodeID = CurrentIR.GetID(CodeNode);
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const uint8_t NumArgs = IR::GetRAArgs(IROp->Op);
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for (uint32_t i = 0; i < NumArgs; ++i) {
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if (IROp->Args[i].IsInvalid()) {
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continue;
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}
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// We do not validate the location of inline constants because it's
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// irrelevant, they're ignored by RA and always inlined to where they
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// need to be. This lets us pool inline constants globally.
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IROps Op = CurrentIR.GetOp<IROp_Header>(IROp->Args[i])->Op;
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if (Op == OP_IRHEADER || Op == OP_INLINECONSTANT) {
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continue;
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}
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OrderedNodeWrapper Arg = IROp->Args[i];
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// If the SSA argument is not defined INSIDE the block, we have
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// cross-block liveness, which we forbid in the IR to simplify RA.
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if (!(Arg.ID() >= BlockIROp->Begin.ID() && Arg.ID() < BlockIROp->Last.ID())) {
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HadError |= true;
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Errors << "Inst %" << CodeID << ": Arg[" << i << "] %" << Arg.ID() << " definition not local!" << std::endl;
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continue;
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}
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// The SSA argument is defined INSIDE this block.
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// It must only be declared prior to this instruction
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// Eg: Valid
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// CodeBlock_1:
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// %_1 = Load
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// %_2 = Load
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// %_3 = <Op> %_1, %_2
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//
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// Eg: Invalid
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// CodeBlock_1:
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// %_1 = Load
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// %_2 = <Op> %_1, %_3
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// %_3 = Load
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if (Arg.ID() > CodeID) {
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HadError |= true;
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Errors << "Inst %" << CodeID << ": Arg[" << i << "] %" << Arg.ID() << " definition does not dominate this use!" << std::endl;
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}
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}
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}
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}
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if (HadError) {
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fextl::stringstream Out;
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FEXCore::IR::Dump(&Out, &CurrentIR, nullptr);
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Out << "Errors:" << std::endl << Errors.str() << std::endl;
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LogMan::Msg::EFmt("{}", Out.str());
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LOGMAN_MSG_A_FMT("Encountered IR validation Error");
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}
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return false;
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}
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fextl::unique_ptr<FEXCore::IR::Pass> CreateValueDominanceValidation() {
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return fextl::make_unique<ValueDominanceValidation>();
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}
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} // namespace FEXCore::IR::Validation
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