mirror of
https://github.com/FEX-Emu/FEX.git
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Alyssa Rosenzweig
bd4464bd5e
Instruction count CI has transformed the way we work on FEX… I love the system and want to make it better. there’s one part of instruction count CI that isn’t so lovable: the problematic “optimal” flag on instructions. There are several issues with this flag, both philosophical and practical. – it is tedious to update the optimal flag when making an implementation optimal. The effect of that is discouraging people from making instructions, optimal, or encouraging people to fail to update the flag, and dilute the value of it. Either way, since we care far more about optimal implementations, then we do about updating the flag, clearly we should prioritize the implementation and not the flag. This issue was not obvious at the outset, when instruction count, CI was introduced, and still quite small. The problem magnified when we started duplicating instructions in bulk for different combinations of CPU features (flagm, AFP, etc.) that intern multiplies the manual work required to update the flags by the corresponding constant factor. if it comes down to a choice between removing this extra coverage and removing the flag, I think we all agree that removing the flag is the lesser evil. – The definition of “optimal” is fundamentally problematic. I have often improved the instruction count of an instruction that was already “optimal”. This is all kinds of silly, and calls into question whether there’s any value whatsoever in the existing classifications of the flag. Furthermore, it is often unknowable, whether an implementation really is optimal. Is it possible to implement BZHI (with flag calculations) in fewer than eight instructions? We don’t know, and it’s silly to pretend that we do. – as a consequence of the problematic definitions , there are so many errors in both directions that I don’t think there’s much value in preserving the existing classification at the expense of +progress. Being able to say “32% of instructions are translated optimally” is neat, but it really doesn’t tell us anything whatsoever when you dig a little deeper. So, as the flag is misleading at best and perhaps harmful at worst, let’s remove it and make the instruction count CI, more useful overall. let’s let the expected count and the assembly speak for themselves, and cut away the chaff. if we want a meaningless number to report to management, we can instead calculate the average blowup factor ;-) Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
220 lines
4.5 KiB
JSON
220 lines
4.5 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [
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"AFP"
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],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256"
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]
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},
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"Instructions": {
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"cvtsi2sd xmm0, eax": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"scvtf d16, w4"
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]
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},
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"cvtsi2sd xmm0, dword [rax]": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"ldr w20, [x4]",
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"scvtf d16, w20"
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]
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},
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"cvtsi2sd xmm0, rax": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"scvtf d16, x4"
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]
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},
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"cvtsi2sd xmm0, qword [rax]": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x4]",
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"scvtf d16, d2"
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]
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},
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"sqrtsd xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x51"
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],
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"ExpectedArm64ASM": [
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"fsqrt d16, d17"
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]
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},
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"addsd xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x58"
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],
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"ExpectedArm64ASM": [
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"fadd d16, d16, d17"
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]
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},
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"mulsd xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x59"
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],
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"ExpectedArm64ASM": [
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"fmul d16, d16, d17"
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]
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},
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"cvtsd2ss xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x5a"
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],
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"ExpectedArm64ASM": [
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"fcvt s16, d17"
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]
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},
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"cvtsd2ss xmm0, [rax]": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x5a"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x4]",
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"fcvt s16, d2"
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]
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},
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"subsd xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x5c"
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],
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"ExpectedArm64ASM": [
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"fsub d16, d16, d17"
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]
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},
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"minsd xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x5d"
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],
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"ExpectedArm64ASM": [
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"fmin d16, d16, d17"
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]
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},
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"divsd xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x5e"
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],
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"ExpectedArm64ASM": [
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"fdiv d16, d16, d17"
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]
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},
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"maxsd xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0x5f"
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],
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"ExpectedArm64ASM": [
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"fmax d16, d16, d17"
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]
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},
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"cmpsd xmm0, xmm1, 0": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
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"fcmeq d16, d16, d17"
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]
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},
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"cmpsd xmm0, xmm1, 1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
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"fcmgt d16, d17, d16"
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]
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},
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"cmpsd xmm0, xmm1, 2": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
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"fcmge d16, d17, d16"
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]
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},
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"cmpsd xmm0, xmm1, 3": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
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"fcmge d0, d16, d17",
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"fcmgt d1, d17, d16",
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"orr v0.8b, v0.8b, v1.8b",
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"mvn v0.8b, v0.8b",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 4": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
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"fcmeq d0, d16, d17",
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"mvn v0.8b, v0.8b",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 5": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
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"fcmgt d2, d17, d16",
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"mvn v2.16b, v2.16b",
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"mov v16.d[0], v2.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 6": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
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"fcmge d2, d17, d16",
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"mvn v2.16b, v2.16b",
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"mov v16.d[0], v2.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 7": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
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"fcmge d0, d16, d17",
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"fcmgt d1, d17, d16",
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"orr v0.8b, v0.8b, v1.8b",
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"mov v16.d[0], v0.d[0]"
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]
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}
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}
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}
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