mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 12:00:17 +02:00
537 lines
13 KiB
JSON
537 lines
13 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [
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"FRINTTS"
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],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"FCMA",
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"AFP"
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],
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"BinaryCacheVersion": 15
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},
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"Instructions": {
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"movsd xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf2 0x0f 0x10",
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"ExpectedArm64ASM": [
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"mov v16.d[0], v17.d[0]"
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]
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},
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"movsd xmm0, [rax]": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf2 0x0f 0x10",
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"ExpectedArm64ASM": [
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"ldr d16, [x4]"
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]
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},
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"movsd [rax], xmm0": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf2 0x0f 0x11",
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"ExpectedArm64ASM": [
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"str d16, [x4]"
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]
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},
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"movddup xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf2 0x0f 0x12",
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"ExpectedArm64ASM": [
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"dup v16.2d, v17.d[0]"
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]
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},
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"movddup xmm0, [rax]": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf2 0x0f 0x12",
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"ExpectedArm64ASM": [
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"ldr d2, [x4]",
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"dup v16.2d, v2.d[0]"
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]
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},
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"cvtsi2sd xmm0, eax": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"scvtf d0, w4",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cvtsi2sd xmm0, dword [rax]": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0xf2 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"ldr w20, [x4]",
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"scvtf d0, w20",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cvtsi2sd xmm0, rax": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"scvtf d0, x4",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cvtsi2sd xmm0, qword [rax]": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0xf2 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x4]",
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"scvtf d0, d2",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"movntsd [rax], xmm0": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf2 0x0f 0x2b",
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"ExpectedArm64ASM": [
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"str d16, [x4]"
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]
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},
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"cvttsd2si eax, xmm0": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf2 0x0f 0x2c",
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"ExpectedArm64ASM": [
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"frint32z d2, d16",
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"fcvtzs w4, d2"
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]
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},
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"cvttsd2si eax, qword [rbx]": {
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"ExpectedInstructionCount": 3,
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"Comment": "0xf2 0x0f 0x2c",
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"ExpectedArm64ASM": [
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"ldr d2, [x6]",
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"frint32z d2, d2",
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"fcvtzs w4, d2"
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]
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},
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"cvttsd2si rax, xmm0": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf2 0x0f 0x2c",
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"ExpectedArm64ASM": [
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"frint64z d2, d16",
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"fcvtzs x4, d2"
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]
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},
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"cvttsd2si rax, qword [rbx]": {
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"ExpectedInstructionCount": 3,
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"Comment": "0xf2 0x0f 0x2c",
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"ExpectedArm64ASM": [
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"ldr d2, [x6]",
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"frint64z d2, d2",
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"fcvtzs x4, d2"
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]
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},
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"cvtsd2si eax, xmm0": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf2 0x0f 0x2d",
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"ExpectedArm64ASM": [
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"frint32x d2, d16",
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"fcvtzs w4, d2"
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]
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},
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"cvtsd2si eax, qword [rbx]": {
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"ExpectedInstructionCount": 3,
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"Comment": "0xf2 0x0f 0x2d",
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"ExpectedArm64ASM": [
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"ldr d2, [x6]",
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"frint32x d2, d2",
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"fcvtzs w4, d2"
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]
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},
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"cvtsd2si rax, xmm0": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf2 0x0f 0x2d",
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"ExpectedArm64ASM": [
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"frint64x d2, d16",
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"fcvtzs x4, d2"
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]
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},
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"cvtsd2si rax, qword [rbx]": {
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"ExpectedInstructionCount": 3,
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"Comment": "0xf2 0x0f 0x2d",
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"ExpectedArm64ASM": [
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"ldr d2, [x6]",
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"frint64x d2, d2",
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"fcvtzs x4, d2"
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]
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},
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"sqrtsd xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x51"
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],
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"ExpectedArm64ASM": [
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"fsqrt d0, d17",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"addsd xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x58"
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],
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"ExpectedArm64ASM": [
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"fadd d0, d16, d17",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"mulsd xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x59"
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],
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"ExpectedArm64ASM": [
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"fmul d0, d16, d17",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cvtsd2ss xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x5a"
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],
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"ExpectedArm64ASM": [
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"fcvt s0, d17",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"cvtsd2ss xmm0, [rax]": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0xf2 0x0f 0x5a"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x4]",
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"fcvt s0, d2",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"subsd xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x5c"
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],
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"ExpectedArm64ASM": [
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"fsub d0, d16, d17",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"minsd xmm0, xmm1": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"0xf2 0x0f 0x5d"
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],
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"ExpectedArm64ASM": [
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"mrs x20, nzcv",
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"fcmp d16, d17",
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"fcsel d0, d16, d17, mi",
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"mov v16.d[0], v0.d[0]",
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"msr nzcv, x20"
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]
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},
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"divsd xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0x5e"
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],
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"ExpectedArm64ASM": [
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"fdiv d0, d16, d17",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"maxsd xmm0, xmm1": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"0xf2 0x0f 0x5f"
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],
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"ExpectedArm64ASM": [
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"mrs x20, nzcv",
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"fcmp d16, d17",
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"fcsel d0, d16, d17, gt",
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"mov v16.d[0], v0.d[0]",
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"msr nzcv, x20"
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]
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},
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"pshuflw xmm0, xmm1, 0": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Broadcast element 0",
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"0xf2 0x0f 0x70"
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],
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"ExpectedArm64ASM": [
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"dup v2.8h, v17.h[0]",
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"trn2 v16.2d, v2.2d, v17.2d"
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]
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},
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"pshuflw xmm0, xmm1, 11100100b": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"Identity copy",
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"0xf2 0x0f 0x70"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b"
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]
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},
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"pshuflw xmm0, xmm1, 01010000b": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"Lower elements Self-zip",
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"0xf2 0x0f 0x70"
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],
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"ExpectedArm64ASM": [
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"ldr x0, [x28, #2720]",
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"ldr q2, [x0, #1280]",
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"tbl v16.16b, {v17.16b}, v2.16b"
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]
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},
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"pshuflw xmm0, xmm1, 1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"Broadcast first element in to Elements 1,2,3",
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"Element 0 gets turned in to element 1",
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"0xf2 0x0f 0x70"
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],
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"ExpectedArm64ASM": [
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"ldr x0, [x28, #2720]",
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"ldr q2, [x0, #16]",
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"tbl v16.16b, {v17.16b}, v2.16b"
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]
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},
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"pshuflw xmm0, xmm1, 0xff": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Broadcast Element 3",
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"0xf2 0x0f 0x70"
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],
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"ExpectedArm64ASM": [
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"dup v2.8h, v17.h[3]",
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"trn2 v16.2d, v2.2d, v17.2d"
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]
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},
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"insertq xmm0, xmm1, 0, 0": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"SSE4a",
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"0xf2 0x0f 0x78"
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],
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"ExpectedArm64ASM": [
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"mov x20, #0xffffffffffffffff",
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"fmov d2, x20",
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"and v3.8b, v17.8b, v2.8b",
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"bic v2.8b, v16.8b, v2.8b",
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"orr v16.8b, v2.8b, v3.8b"
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]
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},
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"insertq xmm0, xmm1, 64, 0": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"SSE4a",
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"0xf2 0x0f 0x78"
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],
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"ExpectedArm64ASM": [
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"mov x20, #0xffffffffffffffff",
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"fmov d2, x20",
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"and v3.8b, v17.8b, v2.8b",
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"bic v2.8b, v16.8b, v2.8b",
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"orr v16.8b, v2.8b, v3.8b"
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]
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},
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"insertq xmm0, xmm1, 32, 32": {
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"ExpectedInstructionCount": 7,
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"Comment": [
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"SSE4a",
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"0xf2 0x0f 0x78"
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],
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"ExpectedArm64ASM": [
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"mov w20, #0xffffffff",
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"fmov d2, x20",
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"and v3.8b, v17.8b, v2.8b",
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"shl v3.2d, v3.2d, #32",
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"shl v2.2d, v2.2d, #32",
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"bic v2.8b, v16.8b, v2.8b",
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"orr v16.8b, v2.8b, v3.8b"
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]
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},
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"insertq xmm0, xmm1": {
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"ExpectedInstructionCount": 19,
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"Comment": [
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"SSE4a",
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"0xf2 0x0f 0x79"
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],
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"ExpectedArm64ASM": [
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"dup v2.2d, v17.d[1]",
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"mov w0, #0x3f",
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"dup v3.2d, x0",
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"and v4.8b, v2.8b, v3.8b",
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"ushr v2.2d, v2.2d, #8",
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"and v2.8b, v2.8b, v3.8b",
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"mov x20, v4.d[0]",
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"mrs x21, nzcv",
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"mov x0, #0xffffffffffffffff",
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"cmp x20, #0x0 (0)",
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"lsl x1, x0, x20",
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"csinv x20, x0, x1, eq",
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"fmov d3, x20",
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"and v4.16b, v17.16b, v3.16b",
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"ushl v4.2d, v4.2d, v2.2d",
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"ushl v3.2d, v3.2d, v2.2d",
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"bic v2.8b, v16.8b, v3.8b",
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"orr v16.8b, v2.8b, v4.8b",
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"msr nzcv, x21"
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]
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},
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"haddps xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf2 0x0f 0x7c",
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"ExpectedArm64ASM": [
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"faddp v16.4s, v16.4s, v17.4s"
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]
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},
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"hsubps xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": "0xf2 0x0f 0x7d",
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"ExpectedArm64ASM": [
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"uzp1 v2.4s, v16.4s, v17.4s",
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"uzp2 v3.4s, v16.4s, v17.4s",
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"fsub v16.4s, v2.4s, v3.4s"
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]
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},
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"cmpsd xmm0, xmm1, 0": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
|
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"fcmeq d0, d17, d16",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 1": {
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"ExpectedInstructionCount": 2,
|
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"Comment": [
|
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"0xf2 0x0f 0xc2"
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],
|
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"ExpectedArm64ASM": [
|
|
"fcmgt d0, d17, d16",
|
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 2": {
|
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"ExpectedInstructionCount": 2,
|
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"Comment": [
|
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"0xf2 0x0f 0xc2"
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],
|
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"ExpectedArm64ASM": [
|
|
"fcmge d0, d17, d16",
|
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 3": {
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"ExpectedInstructionCount": 5,
|
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"Comment": [
|
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"0xf2 0x0f 0xc2"
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],
|
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"ExpectedArm64ASM": [
|
|
"fcmge d0, d16, d17",
|
|
"fcmgt d1, d17, d16",
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"orr v0.8b, v0.8b, v1.8b",
|
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"mvn v0.8b, v0.8b",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 4": {
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"ExpectedInstructionCount": 3,
|
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"Comment": [
|
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"0xf2 0x0f 0xc2"
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],
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"ExpectedArm64ASM": [
|
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"fcmeq d0, d17, d16",
|
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"mvn v0.8b, v0.8b",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 5": {
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"ExpectedInstructionCount": 3,
|
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"Comment": [
|
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"0xf2 0x0f 0xc2"
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],
|
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"ExpectedArm64ASM": [
|
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"fcmgt d2, d17, d16",
|
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"mvn v2.16b, v2.16b",
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"mov v16.d[0], v2.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 6": {
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"ExpectedInstructionCount": 3,
|
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"Comment": [
|
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"0xf2 0x0f 0xc2"
|
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],
|
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"ExpectedArm64ASM": [
|
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"fcmge d2, d17, d16",
|
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"mvn v2.16b, v2.16b",
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"mov v16.d[0], v2.d[0]"
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]
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},
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"cmpsd xmm0, xmm1, 7": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"0xf2 0x0f 0xc2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge d0, d16, d17",
|
|
"fcmgt d1, d17, d16",
|
|
"orr v0.8b, v0.8b, v1.8b",
|
|
"mov v16.d[0], v0.d[0]"
|
|
]
|
|
},
|
|
"addsubps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xf2 0x0f 0xd0",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #3152]",
|
|
"eor v2.16b, v17.16b, v2.16b",
|
|
"fadd v16.4s, v16.4s, v2.4s"
|
|
]
|
|
},
|
|
"movdq2q mm0, xmm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0xf2 0x0f 0xd6",
|
|
"ExpectedArm64ASM": [
|
|
"strb wzr, [x28, #1051]",
|
|
"mov w20, #0xffff",
|
|
"strb w20, [x28, #1202]",
|
|
"str d16, [x28, #1056]",
|
|
"strh w20, [x28, #1064]"
|
|
]
|
|
},
|
|
"cvtpd2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xf2 0x0f 0xe6",
|
|
"ExpectedArm64ASM": [
|
|
"frint32x v2.2d, v17.2d",
|
|
"fcvtzs v2.2d, v2.2d",
|
|
"xtn v16.2s, v2.2d"
|
|
]
|
|
},
|
|
"lddqu xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0xf2 0x0f 0xf0",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]"
|
|
]
|
|
}
|
|
}
|
|
}
|