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Ryan Houdek
acbd920c9a
Only installs the tables if SVE256 isn't supported yet AVX is explicitly enabled with HostFeatures, to protect accidental enablement early. - Only implements 85 instructions starting out - Basic vector moves - Basic vector unary operations - Basic vector binary operations - VZeroUpper/VZeroAll The bulk of the implementation is currently the handling for loading and storing the halves of the registers from the context or from memory. This means the load/store helpers must always return a pair unless only requesting the bottom half of the register, which occurs with 128-bit AVX operations. The store side then needing to consume the named zero register if it occurs since those cases will zero the upper bits. This implementation approach has a few benefits. - I can pound this out extremely quickly - SSE implementations are unaffected and don't need to deal with the insert behaviour of SVE256. - We still keep the SVE256 implementation for the inevitable future when hardware vendors actually do implement it (Give it 8 years or something). - We can actually unit test this path in CI once it is complete. - We can partially optimize some paths with SVE128 (Gathers) and support a full ASIMD path if necessary. One downside is that I can't enable this in CI yet because it can't pass all unittests. but that's a non-issue since it is going to be in heavy flux as I'm hammering out the implementation. It'll get switched on at the end when it's passing all 1265 AVX unittests. Currently at 1001 on this.
FEXCore - Fast x86 Core emulation library
This is the core emulation library that is used for the FEX emulator project. This project aims to provide a fast and functional x86-64 emulation library that can meet and surpass other x86-64 emulation libraries.
Goals
- Be as fast as possible, beating and exceeding current options for x86-64 emulation
- 25% - 50% lower performance than native code would be desired target
- Use an IR to efficiently translate x86-64 to our host architecture
- Support a tiered recompiler to allow for fast runtime performance
- Support offline compilation and offline tooling for inspection and performance analysis
- Support threaded emulation. Including emulating x86-64's strong memory model on weak memory model architectures
- Support a significant portion of the x86-64 instruction space.
- Including MMX, SSE, SSE2, SSE3, SSSE3, and SSE4*
- Support fallback routines for uncommonly used x86-64 instructions
- Including x87 and 3DNow!
- Only support userspace emulation.
- All x86-64 instructions run as if they are under CPL-3(userland) security layer
- Minimal Linux Syscall emulation for testing purposes
- Portable library implementation in order to support easy integration in to applications
Target Host Architecture
The target host architecture for this library is AArch64. Specifically the ARMv8.1 version or newer. The CPU IR is designed with AArch64 in mind but should allow for other architectures as well. x86-64 host support is available for ease of development, but is not a priority.
Not desired
- Kernel space emulation
- CPL0-2 emulation
- Real Mode, Protected Mode, Virtual-8086 Mode, System Management Mode
- IRQs
- SVM
- "Cycle Accurate" emulation