mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 14:00:16 +02:00
8904 lines
236 KiB
JSON
8904 lines
236 KiB
JSON
{
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|
"Features": {
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"Env": {
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"FEX_X87REDUCEDPRECISION": "1"
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},
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"Bitness": 64,
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|
"EnabledHostFeatures": [],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"AFP",
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"FLAGM",
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"FLAGM2"
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|
]
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|
},
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|
"Instructions": {
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|
"fadd dword [rax]": {
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"ExpectedInstructionCount": 7,
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|
"Comment": [
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"0xd8 !11b /0"
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|
],
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|
"ExpectedArm64ASM": [
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|
"ldr s2, [x4]",
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|
"fcvt d2, s2",
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|
"ldrb w20, [x28, #1051]",
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|
"add x20, x28, x20, lsl #4",
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|
"ldr d3, [x20, #1056]",
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|
"fadd d2, d3, d2",
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"str d2, [x20, #1056]"
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]
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},
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"fmul dword [rax]": {
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"ExpectedInstructionCount": 7,
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|
"Comment": [
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|
"0xd8 !11b /1"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
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|
"fcvt d2, s2",
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|
"ldrb w20, [x28, #1051]",
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|
"add x20, x28, x20, lsl #4",
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"ldr d3, [x20, #1056]",
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"fmul d2, d3, d2",
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|
"str d2, [x20, #1056]"
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]
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},
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|
"fcom dword [rax]": {
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|
"ExpectedInstructionCount": 17,
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|
"Comment": [
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|
"0xd8 !11b /2"
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|
],
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|
"ExpectedArm64ASM": [
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|
"ldr s2, [x4]",
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|
"fcvt d2, s2",
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|
"mrs x20, nzcv",
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|
"ldrb w21, [x28, #1051]",
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|
"add x21, x28, x21, lsl #4",
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|
"ldr d3, [x21, #1056]",
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"fcmp d3, d2",
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"cset x21, vs",
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"cset x22, lo",
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"cset x23, eq",
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"orr w22, w22, w21",
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"orr w23, w23, w21",
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"strb w22, [x28, #1048]",
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"strb wzr, [x28, #1049]",
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"strb w21, [x28, #1050]",
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"strb w23, [x28, #1054]",
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"msr nzcv, x20"
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]
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},
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"fcomp dword [rax]": {
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"ExpectedInstructionCount": 25,
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|
"Comment": [
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|
"0xd8 !11b /3"
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|
],
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|
"ExpectedArm64ASM": [
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|
"ldr s2, [x4]",
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|
"fcvt d2, s2",
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|
"mrs x20, nzcv",
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|
"ldrb w21, [x28, #1051]",
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|
"add x22, x28, x21, lsl #4",
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"ldr d3, [x22, #1056]",
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"fcmp d3, d2",
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"cset x22, vs",
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"cset x23, lo",
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"cset x24, eq",
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"orr w23, w23, w22",
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"orr w24, w24, w22",
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"strb w23, [x28, #1048]",
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"strb wzr, [x28, #1049]",
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"strb w22, [x28, #1050]",
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"strb w24, [x28, #1054]",
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|
"add w22, w21, #0x1 (1)",
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|
"and w22, w22, #0x7",
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"msr nzcv, x20",
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"strb w22, [x28, #1051]",
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"ldrb w20, [x28, #1202]",
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"mov w22, #0x1",
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"lsl w21, w22, w21",
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"bic w20, w20, w21",
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"strb w20, [x28, #1202]"
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]
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|
},
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|
"fsub dword [rax]": {
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|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xd8 !11b /4"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"fcvt d2, s2",
|
|
"ldrb w20, [x28, #1051]",
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|
"add x20, x28, x20, lsl #4",
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"ldr d3, [x20, #1056]",
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"fsub d2, d3, d2",
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|
"str d2, [x20, #1056]"
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]
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},
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"fsubr dword [rax]": {
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"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xd8 !11b /5"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"fcvt d2, s2",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
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|
"fsub d2, d2, d3",
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|
"str d2, [x20, #1056]"
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|
]
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|
},
|
|
"fdiv dword [rax]": {
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"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xd8 !11b /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"fcvt d2, s2",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
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|
"str d2, [x20, #1056]"
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|
]
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|
},
|
|
"fdivr dword [rax]": {
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"ExpectedInstructionCount": 7,
|
|
"Comment": [
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|
"0xd8 !11b /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"fcvt d2, s2",
|
|
"ldrb w20, [x28, #1051]",
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|
"add x20, x28, x20, lsl #4",
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|
"ldr d3, [x20, #1056]",
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"fdiv d2, d2, d3",
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"str d2, [x20, #1056]"
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|
]
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},
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"fadd st0, st0": {
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"ExpectedInstructionCount": 5,
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|
"Comment": [
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"0xd8 11b 0xc0 /0"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
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|
"fadd d2, d2, d2",
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"str d2, [x20, #1056]"
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]
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},
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"fadd st0, st1": {
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|
"ExpectedInstructionCount": 9,
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|
"Comment": [
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"0xd8 11b 0xc1 /0"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
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|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
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|
"add x20, x28, x20, lsl #4",
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"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
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|
"str d2, [x20, #1056]"
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|
]
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|
},
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"fadd st0, st2": {
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|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xc2 /0"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
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|
"str d2, [x20, #1056]"
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|
]
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|
},
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"fadd st0, st3": {
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|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xc3 /0"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
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|
"add x20, x28, x20, lsl #4",
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"ldr d3, [x20, #1056]",
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"fadd d2, d3, d2",
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|
"str d2, [x20, #1056]"
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|
]
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|
},
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"fadd st0, st4": {
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|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xc4 /0"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
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|
]
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|
},
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|
"fadd st0, st5": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xc5 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
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|
]
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|
},
|
|
"fadd st0, st6": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xc6 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fadd st0, st7": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xc7 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st0, st0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd8 11b 0xc8 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fmul d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st0, st1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xc9 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st0, st2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xca /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st0, st3": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xcb /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st0, st4": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xcc /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st0, st5": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xcd /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st0, st6": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xce /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st0, st7": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xcf /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcom st0, st0": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xd8 11b 0xd0 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"mrs x20, nzcv",
|
|
"fcmp d2, d2",
|
|
"cset x21, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w21",
|
|
"orr w23, w23, w21",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w21, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"fcom st0, st1": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xd8 11b 0xd1 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fcom st0, st2": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xd8 11b 0xd2 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fcom st0, st3": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xd8 11b 0xd3 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fcom st0, st4": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xd8 11b 0xd4 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fcom st0, st5": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xd8 11b 0xd5 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fcom st0, st6": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xd8 11b 0xd6 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fcom st0, st7": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xd8 11b 0xd7 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fcomp st0, st0": {
|
|
"ExpectedInstructionCount": 23,
|
|
"Comment": [
|
|
"0xd8 11b 0xd8 /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"fcmp d2, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomp st0, st1": {
|
|
"ExpectedInstructionCount": 25,
|
|
"Comment": [
|
|
"0xd8 11b 0xd9 /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"mrs x22, nzcv",
|
|
"add x23, x28, x20, lsl #4",
|
|
"ldr d3, [x23, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x23, vs",
|
|
"cset x24, lo",
|
|
"cset x30, eq",
|
|
"orr w24, w24, w23",
|
|
"orr w30, w30, w23",
|
|
"strb w24, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w23, [x28, #1050]",
|
|
"strb w30, [x28, #1054]",
|
|
"msr nzcv, x22",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomp st0, st2": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xd8 11b 0xda /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomp st0, st3": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xd8 11b 0xdb /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomp st0, st4": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xd8 11b 0xdc /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomp st0, st5": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xd8 11b 0xdd /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomp st0, st6": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xd8 11b 0xde /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomp st0, st7": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xd8 11b 0xdf /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsub st0, st0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd8 11b 0xe0 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fsub d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st0, st1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xe1 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st0, st2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xe2 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st0, st3": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xe3 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st0, st4": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xe4 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st0, st5": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xe5 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st0, st6": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xe6 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st0, st7": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xe7 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsubr st0, st0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd8 11b 0xe8 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fsub d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsubr st0, st1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xe9 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st0, st2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xea /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st0, st3": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xeb /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x3 (3)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st0, st4": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xec /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st0, st5": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xed /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st0, st6": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xee /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st0, st7": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xef /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdiv st0, st0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd8 11b 0xf0 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fdiv d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st0, st1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xf1 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st0, st2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xf2 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st0, st3": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xf3 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st0, st4": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xf4 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st0, st5": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xf5 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st0, st6": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xf6 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st0, st7": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xf7 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdivr st0, st0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd8 11b 0xf8 /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fdiv d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdivr st0, st1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xf9 /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st0, st2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xfa /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st0, st3": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xfb /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x3 (3)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st0, st4": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xfc /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st0, st5": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xfd /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st0, st6": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xfe /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st0, st7": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xd8 11b 0xff /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fld dword [rax]": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xd9 !11b /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"fcvt d2, s2",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fst dword [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd9 !11b /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fcvt s2, d2",
|
|
"str s2, [x4]"
|
|
]
|
|
},
|
|
"fstp dword [rax]": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xd9 !11b /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fcvt s2, d2",
|
|
"str s2, [x4]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fldenv [rax]": {
|
|
"ExpectedInstructionCount": 33,
|
|
"Comment": [
|
|
"0xd9 !11b /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"ubfx w21, w20, #10, #3",
|
|
"rbit w1, w21",
|
|
"lsr w1, w1, #30",
|
|
"mrs x0, fpcr",
|
|
"bfi x0, x1, #22, #2",
|
|
"lsr x1, x21, #2",
|
|
"bfi x0, x1, #24, #1",
|
|
"msr fpcr, x0",
|
|
"strh w20, [x28, #1200]",
|
|
"ldr w20, [x4, #4]",
|
|
"ubfx w21, w20, #11, #3",
|
|
"strb w21, [x28, #1051]",
|
|
"ubfx w21, w20, #8, #1",
|
|
"ubfx w22, w20, #9, #1",
|
|
"ubfx w23, w20, #10, #1",
|
|
"ubfx w24, w20, #14, #1",
|
|
"ubfx w20, w20, #0, #1",
|
|
"strb w21, [x28, #1048]",
|
|
"strb w22, [x28, #1049]",
|
|
"strb w23, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"strb w20, [x28, #1040]",
|
|
"ldr w20, [x4, #8]",
|
|
"and w20, w20, w20, lsr #1",
|
|
"mov w21, #0x55555555",
|
|
"bic w20, w21, w20",
|
|
"orr w20, w20, w20, lsr #1",
|
|
"and w20, w20, #0x33333333",
|
|
"orr w20, w20, w20, lsr #2",
|
|
"and w20, w20, #0xf0f0f0f",
|
|
"orr w20, w20, w20, lsr #4",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fldcw [rax]": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xd9 !11b /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"ubfx w21, w20, #10, #3",
|
|
"rbit w1, w21",
|
|
"lsr w1, w1, #30",
|
|
"mrs x0, fpcr",
|
|
"bfi x0, x1, #22, #2",
|
|
"lsr x1, x21, #2",
|
|
"bfi x0, x1, #24, #1",
|
|
"msr fpcr, x0",
|
|
"strh w20, [x28, #1200]"
|
|
]
|
|
},
|
|
"fnstenv [rax]": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": [
|
|
"0xd9 !11b /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x28, #1200]",
|
|
"str w20, [x4]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"lsl x20, x20, #11",
|
|
"ldrb w21, [x28, #1048]",
|
|
"orr x20, x20, x21, lsl #8",
|
|
"ldrb w21, [x28, #1049]",
|
|
"orr x20, x20, x21, lsl #9",
|
|
"ldrb w21, [x28, #1050]",
|
|
"orr x20, x20, x21, lsl #10",
|
|
"ldrb w21, [x28, #1054]",
|
|
"orr x20, x20, x21, lsl #14",
|
|
"ldrb w21, [x28, #1040]",
|
|
"orr x20, x20, x21",
|
|
"str w20, [x4, #4]",
|
|
"ldrb w20, [x28, #1202]",
|
|
"orr w20, w20, w20, lsl #4",
|
|
"and w20, w20, #0xf0f0f0f",
|
|
"orr w20, w20, w20, lsl #2",
|
|
"and w20, w20, #0x33333333",
|
|
"orr w20, w20, w20, lsl #1",
|
|
"and w20, w20, #0x55555555",
|
|
"orr w20, w20, w20, lsl #1",
|
|
"eor w20, w20, #0xffff",
|
|
"str w20, [x4, #8]",
|
|
"str wzr, [x4, #12]",
|
|
"str wzr, [x4, #16]",
|
|
"str wzr, [x4, #20]",
|
|
"str wzr, [x4, #24]"
|
|
]
|
|
},
|
|
"fnstcw [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0xd9 !11b /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x28, #1200]",
|
|
"strh w20, [x4]"
|
|
]
|
|
},
|
|
"fld st0": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xd9 11b 0xc0 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fld st1": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xd9 11b 0xc1 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fld st2": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xd9 11b 0xc2 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fld st3": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xd9 11b 0xc3 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fld st4": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xd9 11b 0xc4 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fld st5": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xd9 11b 0xc5 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fld st6": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xd9 11b 0xc6 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fld st7": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xd9 11b 0xc7 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"strb w20, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fxch st0, st0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0xd9 11b 0xc8 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"strb wzr, [x28, #1049]"
|
|
]
|
|
},
|
|
"fxch st0, st1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xd9 11b 0xc9 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"str d3, [x21, #1056]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fxch st0, st2": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xd9 11b 0xca /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"str d3, [x21, #1056]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fxch st0, st3": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xd9 11b 0xcb /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x3 (3)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"str d3, [x21, #1056]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fxch st0, st4": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xd9 11b 0xcc /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"str d3, [x21, #1056]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fxch st0, st5": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xd9 11b 0xcd /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"str d3, [x21, #1056]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fxch st0, st6": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xd9 11b 0xce /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"str d3, [x21, #1056]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fxch st0, st7": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xd9 11b 0xcf /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"str d3, [x21, #1056]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fnop": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Comment": [
|
|
"0xd9 11b 0xd0 /2"
|
|
],
|
|
"ExpectedArm64ASM": []
|
|
},
|
|
"fchs": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd9 11b 0xe0 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fneg v2.2d, v2.2d",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fabs": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd9 11b 0xe1 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fabs d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"ftst": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xd9 11b 0xe4 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mrs x20, nzcv",
|
|
"ldrb w21, [x28, #1051]",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mov w21, #0x0",
|
|
"fmov d3, x21",
|
|
"fcmp d2, d3",
|
|
"cset x21, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w21",
|
|
"orr w23, w23, w21",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w21, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"fxam": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xe5 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mov x21, v2.d[0]",
|
|
"lsr x21, x21, #63",
|
|
"strb w21, [x28, #1049]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"lsr w20, w21, w20",
|
|
"and w20, w20, #0x1",
|
|
"mrs x21, nzcv",
|
|
"cmp w20, #0x1 (1)",
|
|
"cset x22, ne",
|
|
"strb w22, [x28, #1048]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w22, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fld1": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xd9 11b 0xe8 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0x3ff0000000000000",
|
|
"fmov d2, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fldl2t": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xe9 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xa372",
|
|
"movk x20, #0x979, lsl #16",
|
|
"movk x20, #0x934f, lsl #32",
|
|
"movk x20, #0x400a, lsl #48",
|
|
"fmov d2, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fldl2e": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xea /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0x82fe",
|
|
"movk x20, #0x652b, lsl #16",
|
|
"movk x20, #0x1547, lsl #32",
|
|
"movk x20, #0x3ff7, lsl #48",
|
|
"fmov d2, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fldpi": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xeb /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0x2d18",
|
|
"movk x20, #0x5444, lsl #16",
|
|
"movk x20, #0x21fb, lsl #32",
|
|
"movk x20, #0x4009, lsl #48",
|
|
"fmov d2, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fldlg2": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xec /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0x79ff",
|
|
"movk x20, #0x509f, lsl #16",
|
|
"movk x20, #0x4413, lsl #32",
|
|
"movk x20, #0x3fd3, lsl #48",
|
|
"fmov d2, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fldln2": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xed /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0x39ef",
|
|
"movk x20, #0xfefa, lsl #16",
|
|
"movk x20, #0x2e42, lsl #32",
|
|
"movk x20, #0x3fe6, lsl #48",
|
|
"fmov d2, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fldz": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xd9 11b 0xee /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x0",
|
|
"fmov d2, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"f2xm1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xd9 11b 0xf0 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #3056]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fyl2x": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xf1 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmov d0, d3",
|
|
"fmov d1, d2",
|
|
"ldr x0, [x28, #3080]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x22, #1056]"
|
|
]
|
|
},
|
|
"fptan": {
|
|
"ExpectedInstructionCount": 23,
|
|
"Comment": [
|
|
"0xd9 11b 0xf2 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #3048]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"mov x22, #0x3ff0000000000000",
|
|
"fmov d3, x22",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb wzr, [x28, #1050]",
|
|
"strb w20, [x28, #1051]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"str d3, [x22, #1056]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fpatan": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xf3 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fmov d0, d3",
|
|
"fmov d1, d2",
|
|
"ldr x0, [x28, #3072]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"strb w20, [x28, #1051]",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fxtract": {
|
|
"ExpectedInstructionCount": 40,
|
|
"Comment": [
|
|
"0xd9 11b 0xf4 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mov x22, v2.d[0]",
|
|
"mov x23, #0xfff0000000000000",
|
|
"fmov d3, x23",
|
|
"mov x23, #0x7ff0000000000000",
|
|
"fmov d4, x23",
|
|
"ubfx x23, x22, #52, #11",
|
|
"sub x23, x23, #0x3ff (1023)",
|
|
"scvtf d5, x23",
|
|
"and x23, x22, #0x800fffffffffffff",
|
|
"orr x23, x23, #0x3ff0000000000000",
|
|
"fmov d6, x23",
|
|
"mrs x23, nzcv",
|
|
"and x24, x22, #0xfffffffffffff",
|
|
"mov x30, #0xffffffffffffffff",
|
|
"tst x24, x30",
|
|
"fcsel d4, d4, d2, eq",
|
|
"ubfx x24, x22, #52, #11",
|
|
"cmp x24, #0x7ff (2047)",
|
|
"fcsel d4, d4, d5, eq",
|
|
"fcsel d5, d2, d6, eq",
|
|
"tst x22, #0x7fffffffffffffff",
|
|
"fcsel d2, d2, d5, eq",
|
|
"fcsel d3, d3, d4, eq",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"msr nzcv, x23",
|
|
"strb w20, [x28, #1051]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"str d2, [x22, #1056]",
|
|
"str d3, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x8",
|
|
"sub w20, w22, w20",
|
|
"mov w22, #0x303",
|
|
"lsr w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fprem1": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xf5 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmov d0, d3",
|
|
"fmov d1, d2",
|
|
"ldr x0, [x28, #3104]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"strb wzr, [x28, #1050]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdecstp": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xd9 11b 0xf6 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"fincstp": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xd9 11b 0xf7 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"fprem": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xf8 /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmov d0, d3",
|
|
"fmov d1, d2",
|
|
"ldr x0, [x28, #3096]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"strb wzr, [x28, #1050]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fyl2xp1": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xd9 11b 0xf9 /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmov d0, d3",
|
|
"fmov d1, d2",
|
|
"ldr x0, [x28, #3088]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x22, #1056]"
|
|
]
|
|
},
|
|
"fsqrt": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd9 11b 0xfa /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fsqrt d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsincos": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xd9 11b 0xfb /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #3032]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d3, d0",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #3040]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb wzr, [x28, #1050]",
|
|
"strb w20, [x28, #1051]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"str d2, [x22, #1056]",
|
|
"str d3, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"frndint": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xd9 11b 0xfc /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"frinti d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fscale": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xd9 11b 0xfd /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmov d0, d3",
|
|
"fmov d1, d2",
|
|
"ldr x0, [x28, #3064]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsin": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xd9 11b 0xfe /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #3032]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"strb wzr, [x28, #1050]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcos": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xd9 11b 0xff /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #3040]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"strb wzr, [x28, #1050]",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fiadd dword [rax]": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xda !11b /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fimul dword [rax]": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xda !11b /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"ficom dword [rax]": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xda !11b /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"scvtf d2, w20",
|
|
"mrs x20, nzcv",
|
|
"ldrb w21, [x28, #1051]",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x21, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w21",
|
|
"orr w23, w23, w21",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w21, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ficomp dword [rax]": {
|
|
"ExpectedInstructionCount": 25,
|
|
"Comment": [
|
|
"0xda !11b /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"scvtf d2, w20",
|
|
"mrs x20, nzcv",
|
|
"ldrb w21, [x28, #1051]",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w21, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x20",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w20, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w21, w22, w21",
|
|
"bic w20, w20, w21",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fisub dword [rax]": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xda !11b /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fisubr dword [rax]": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xda !11b /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d2, d3",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fidiv dword [rax]": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xda !11b /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fidivr dword [rax]": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xda !11b /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d2, d3",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovb st0, st0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xda 11b 0xc0 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, lo",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v3.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovb st0, st1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xc1 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, lo",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovb st0, st2": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xc2 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, lo",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovb st0, st3": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xc3 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, lo",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovb st0, st4": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xc4 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, lo",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovb st0, st5": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xc5 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, lo",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovb st0, st6": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xc6 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, lo",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovb st0, st7": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xc7 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, lo",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmove st0, st0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xda 11b 0xc8 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, eq",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v3.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmove st0, st1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xc9 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, eq",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmove st0, st2": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xca /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, eq",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmove st0, st3": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xcb /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, eq",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmove st0, st4": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xcc /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, eq",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmove st0, st5": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xcd /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, eq",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmove st0, st6": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xce /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, eq",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmove st0, st7": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xcf /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, eq",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovbe st0, st0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xda 11b 0xd0 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ls",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v3.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovbe st0, st1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xd1 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ls",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovbe st0, st2": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xd2 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ls",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovbe st0, st3": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xd3 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ls",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovbe st0, st4": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xd4 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ls",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovbe st0, st5": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xd5 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ls",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovbe st0, st6": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xd6 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ls",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovbe st0, st7": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xda 11b 0xd7 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ls",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovu st0, st0": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xda 11b 0xd8 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v3.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovu st0, st1": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xda 11b 0xd9 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovu st0, st2": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xda 11b 0xda /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovu st0, st3": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xda 11b 0xdb /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovu st0, st4": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xda 11b 0xdc /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovu st0, st5": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xda 11b 0xdd /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovu st0, st6": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xda 11b 0xde /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovu st0, st7": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xda 11b 0xdf /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fucompp": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": [
|
|
"0xda 11b 0xe9 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"mrs x22, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w20",
|
|
"orr w24, w24, w20",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w20, w21, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"msr nzcv, x22",
|
|
"strb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x8",
|
|
"sub w20, w22, w20",
|
|
"mov w22, #0xc0c0",
|
|
"lsr w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fild dword [rax]": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xdf !11b /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fisttp dword [rax]": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xdb !11b /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fcvtzs w21, d2",
|
|
"str w21, [x4]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fist dword [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xdb !11b /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"frinti d0, d2",
|
|
"fcvtzs w20, d0",
|
|
"str w20, [x4]"
|
|
]
|
|
},
|
|
"fistp dword [rax]": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdf !11b /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"frinti d0, d2",
|
|
"fcvtzs w21, d0",
|
|
"str w21, [x4]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fld tword [rax]": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Comment": [
|
|
"0xdb !11b /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"add x20, x4, #0x8 (8)",
|
|
"ld1 {v2.h}[4], [x20]",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v2.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fstp tword [rax]": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Comment": [
|
|
"0xdb !11b /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"str d2, [x4]",
|
|
"mov x21, v2.d[1]",
|
|
"strh w21, [x4, #8]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcmovnb st0, st0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xdb 11b 0xc0 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hs",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v3.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnb st0, st1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xc1 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hs",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnb st0, st2": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xc2 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hs",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnb st0, st3": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xc3 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hs",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnb st0, st4": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xc4 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hs",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnb st0, st5": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xc5 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hs",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnb st0, st6": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xc6 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hs",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnb st0, st7": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xc7 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hs",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovne st0, st0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xdb 11b 0xc8 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ne",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v3.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovne st0, st1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xc9 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ne",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovne st0, st2": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xca /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ne",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovne st0, st3": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xcb /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ne",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovne st0, st4": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xcc /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ne",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovne st0, st5": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xcd /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ne",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovne st0, st6": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xce /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ne",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovne st0, st7": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xcf /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, ne",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnbe st0, st0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xdb 11b 0xd0 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hi",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v3.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnbe st0, st1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xd1 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hi",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnbe st0, st2": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xd2 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hi",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnbe st0, st3": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xd3 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hi",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnbe st0, st4": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xd4 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hi",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnbe st0, st5": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xd5 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hi",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnbe st0, st6": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xd6 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hi",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnbe st0, st7": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xd7 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"csetm x20, hi",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnu st0, st0": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"0xdb 11b 0xd8 /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v3.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnu st0, st1": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdb 11b 0xd9 /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnu st0, st2": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdb 11b 0xda /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnu st0, st3": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdb 11b 0xdb /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnu st0, st4": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdb 11b 0xdc /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnu st0, st5": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdb 11b 0xdd /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnu st0, st6": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdb 11b 0xde /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcmovnu st0, st7": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdb 11b 0xdf /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"sbfx x20, x20, #0, #1",
|
|
"dup v2.2d, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d4, [x20, #1056]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fnclex": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0xdb 11b 0xe2 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"strb wzr, [x28, #1040]"
|
|
]
|
|
},
|
|
"fninit": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xdb 11b 0xe3 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x0",
|
|
"rbit w1, w20",
|
|
"lsr w1, w1, #30",
|
|
"mrs x0, fpcr",
|
|
"bfi x0, x1, #22, #2",
|
|
"lsr x1, x20, #2",
|
|
"bfi x0, x1, #24, #1",
|
|
"msr fpcr, x0",
|
|
"mov w20, #0x37f",
|
|
"strh w20, [x28, #1200]",
|
|
"strb wzr, [x28, #1051]",
|
|
"strb wzr, [x28, #1202]",
|
|
"strb wzr, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb wzr, [x28, #1050]",
|
|
"strb wzr, [x28, #1054]",
|
|
"strb wzr, [x28, #1040]"
|
|
]
|
|
},
|
|
"fucomi st0, st0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xdb 11b 0xe8 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fcmp d2, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fucomi st0, st1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xe9 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fucomi st0, st2": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xea /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fucomi st0, st3": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xeb /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fucomi st0, st4": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xec /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fucomi st0, st5": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xed /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fucomi st0, st6": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xee /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fucomi st0, st7": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xef /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fcomi st0, st0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0xdb 11b 0xf0 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fcmp d2, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fcomi st0, st1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xf1 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fcomi st0, st2": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xf2 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fcomi st0, st3": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xf3 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fcomi st0, st4": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xf4 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fcomi st0, st5": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xf5 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fcomi st0, st6": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xf6 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fcomi st0, st7": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdb 11b 0xf7 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"fadd qword [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xdc !11b /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul qword [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xdc !11b /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fcom qword [rax]": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xdc !11b /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"mrs x20, nzcv",
|
|
"ldrb w21, [x28, #1051]",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x21, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w21",
|
|
"orr w23, w23, w21",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w21, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"fcomp qword [rax]": {
|
|
"ExpectedInstructionCount": 24,
|
|
"Comment": [
|
|
"0xdc !11b /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"mrs x20, nzcv",
|
|
"ldrb w21, [x28, #1051]",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w21, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x20",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w20, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w21, w22, w21",
|
|
"bic w20, w20, w21",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsub qword [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xdc !11b /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsubr qword [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xdc !11b /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d2, d3",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv qword [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xdc !11b /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdivr qword [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xdc !11b /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d2, d3",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"db 0xdc, 0xc0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"fadd st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xdc 11b 0xc0 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fadd d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fadd st1, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xc1 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fadd st2, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xc2 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fadd st3, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xc3 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x3 (3)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fadd st4, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xc4 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fadd st5, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xc5 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fadd st6, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xc6 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fadd st7, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xc7 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"db 0xdc, 0xc8": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"fmul st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xdc 11b 0xc8 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fmul d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st1, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xc9 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st2, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xca /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st3, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xcb /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x3 (3)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st4, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xcc /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st5, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xcd /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st6, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xce /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fmul st7, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xcf /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"db 0xdc, 0xe0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"fsubr st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xdc 11b 0xe0 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fsub d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsubr st1, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xe1 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st2, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xe2 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st3, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xe3 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st4, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xe4 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st5, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xe5 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st6, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xe6 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fsubr st7, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xe7 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"db 0xdc, 0xe8": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"fsub st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xdc 11b 0xe8 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fsub d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st1, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xe9 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st2, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xea /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st3, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xeb /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x3 (3)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st4, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xec /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st5, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xed /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st6, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xee /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fsub st7, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xef /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"db 0xdc, 0xf0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"fdivr st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xdc 11b 0xf0 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fdiv d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdivr st1, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xf1 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st2, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xf2 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st3, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xf3 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st4, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xf4 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st5, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xf5 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st6, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xf6 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"fdivr st7, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xf7 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x21, #1056]"
|
|
]
|
|
},
|
|
"db 0xdc, 0xf8": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"fdiv st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xdc 11b 0xf8 /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"fdiv d2, d2, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st1, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xf9 /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st2, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xfa /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st3, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xfb /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x3 (3)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st4, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xfc /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st5, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xfd /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st6, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xfe /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fdiv st7, st0": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0xdc 11b 0xff /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fld qword [rax]": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xdd !11b /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fisttp qword [rax]": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xdd !11b /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fcvtzs v2.2d, v2.2d",
|
|
"str d2, [x4]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fst qword [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xdd !11b /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"str d2, [x4]"
|
|
]
|
|
},
|
|
"fstp qword [rax]": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xdd !11b /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"str d2, [x4]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"frstor [rax]": {
|
|
"ExpectedInstructionCount": 141,
|
|
"Comment": [
|
|
"0xdd !11b /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"strh w20, [x28, #1200]",
|
|
"lsr w20, w20, #10",
|
|
"and w20, w20, #0x3",
|
|
"rbit w1, w20",
|
|
"lsr w1, w1, #30",
|
|
"mrs x0, fpcr",
|
|
"bfi x0, x1, #22, #2",
|
|
"lsr x1, x20, #2",
|
|
"bfi x0, x1, #24, #1",
|
|
"msr fpcr, x0",
|
|
"ldr w20, [x4, #4]",
|
|
"ubfx w21, w20, #11, #3",
|
|
"strb w21, [x28, #1051]",
|
|
"ubfx w22, w20, #8, #1",
|
|
"ubfx w23, w20, #9, #1",
|
|
"ubfx w24, w20, #10, #1",
|
|
"ubfx w30, w20, #14, #1",
|
|
"ubfx w20, w20, #0, #1",
|
|
"strb w22, [x28, #1048]",
|
|
"strb w23, [x28, #1049]",
|
|
"strb w24, [x28, #1050]",
|
|
"strb w30, [x28, #1054]",
|
|
"strb w20, [x28, #1040]",
|
|
"ldr w20, [x4, #8]",
|
|
"and w20, w20, w20, lsr #1",
|
|
"mov w22, #0x55555555",
|
|
"bic w20, w22, w20",
|
|
"orr w20, w20, w20, lsr #1",
|
|
"and w20, w20, #0x33333333",
|
|
"orr w20, w20, w20, lsr #2",
|
|
"and w20, w20, #0xf0f0f0f",
|
|
"orr w20, w20, w20, lsr #4",
|
|
"strb w20, [x28, #1202]",
|
|
"mov x20, #0xffffffffffffffff",
|
|
"mov w22, #0xffff",
|
|
"fmov d2, x20",
|
|
"fmov v2.D[1], x22",
|
|
"ldur q3, [x4, #28]",
|
|
"and v3.16b, v3.16b, v2.16b",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v3.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d3, d0",
|
|
"add x0, x28, x21, lsl #4",
|
|
"str d3, [x0, #1056]",
|
|
"add w20, w21, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"ldur q3, [x4, #38]",
|
|
"and v3.16b, v3.16b, v2.16b",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v3.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d3, d0",
|
|
"add x0, x28, x20, lsl #4",
|
|
"str d3, [x0, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"ldr q3, [x4, #48]",
|
|
"and v3.16b, v3.16b, v2.16b",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v3.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d3, d0",
|
|
"add x0, x28, x20, lsl #4",
|
|
"str d3, [x0, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"ldur q3, [x4, #58]",
|
|
"and v3.16b, v3.16b, v2.16b",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v3.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d3, d0",
|
|
"add x0, x28, x20, lsl #4",
|
|
"str d3, [x0, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"ldur q3, [x4, #68]",
|
|
"and v3.16b, v3.16b, v2.16b",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v3.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d3, d0",
|
|
"add x0, x28, x20, lsl #4",
|
|
"str d3, [x0, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"ldur q3, [x4, #78]",
|
|
"and v3.16b, v3.16b, v2.16b",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v3.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d3, d0",
|
|
"add x0, x28, x20, lsl #4",
|
|
"str d3, [x0, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"ldur q3, [x4, #88]",
|
|
"and v2.16b, v3.16b, v2.16b",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v2.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"add x0, x28, x20, lsl #4",
|
|
"str d2, [x0, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"ldur d2, [x4, #98]",
|
|
"ldr h3, [x4, #106]",
|
|
"mov v2.h[4], v3.h[0]",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v2.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"add x0, x28, x20, lsl #4",
|
|
"str d2, [x0, #1056]"
|
|
]
|
|
},
|
|
"fnsave [rax]": {
|
|
"ExpectedInstructionCount": 143,
|
|
"Comment": [
|
|
"0xdd !11b /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrh w21, [x28, #1200]",
|
|
"str w21, [x4]",
|
|
"ldrb w21, [x28, #1051]",
|
|
"lsl x21, x21, #11",
|
|
"ldrb w22, [x28, #1048]",
|
|
"orr x21, x21, x22, lsl #8",
|
|
"ldrb w22, [x28, #1049]",
|
|
"orr x21, x21, x22, lsl #9",
|
|
"ldrb w22, [x28, #1050]",
|
|
"orr x21, x21, x22, lsl #10",
|
|
"ldrb w22, [x28, #1054]",
|
|
"orr x21, x21, x22, lsl #14",
|
|
"ldrb w22, [x28, #1040]",
|
|
"orr x21, x21, x22",
|
|
"str w21, [x4, #4]",
|
|
"mov w21, #0x0",
|
|
"ldrb w22, [x28, #1202]",
|
|
"orr w22, w22, w22, lsl #4",
|
|
"and w22, w22, #0xf0f0f0f",
|
|
"orr w22, w22, w22, lsl #2",
|
|
"and w22, w22, #0x33333333",
|
|
"orr w22, w22, w22, lsl #1",
|
|
"and w22, w22, #0x55555555",
|
|
"orr w22, w22, w22, lsl #1",
|
|
"eor w22, w22, #0xffff",
|
|
"str w22, [x4, #8]",
|
|
"str wzr, [x4, #12]",
|
|
"str wzr, [x4, #16]",
|
|
"str wzr, [x4, #20]",
|
|
"str wzr, [x4, #24]",
|
|
"add x0, x28, x20, lsl #4",
|
|
"ldr d2, [x0, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"stur q2, [x4, #28]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x0, x28, x20, lsl #4",
|
|
"ldr d2, [x0, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"stur q2, [x4, #38]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x0, x28, x20, lsl #4",
|
|
"ldr d2, [x0, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"str q2, [x4, #48]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x0, x28, x20, lsl #4",
|
|
"ldr d2, [x0, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"stur q2, [x4, #58]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x0, x28, x20, lsl #4",
|
|
"ldr d2, [x0, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"stur q2, [x4, #68]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x0, x28, x20, lsl #4",
|
|
"ldr d2, [x0, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"stur q2, [x4, #78]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x0, x28, x20, lsl #4",
|
|
"ldr d2, [x0, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"stur q2, [x4, #88]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x0, x28, x20, lsl #4",
|
|
"ldr d2, [x0, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"stur d2, [x4, #98]",
|
|
"dup v2.8h, v2.h[4]",
|
|
"str h2, [x4, #106]",
|
|
"rbit w1, w21",
|
|
"lsr w1, w1, #30",
|
|
"mrs x0, fpcr",
|
|
"bfi x0, x1, #22, #2",
|
|
"lsr x1, x21, #2",
|
|
"bfi x0, x1, #24, #1",
|
|
"msr fpcr, x0",
|
|
"mov w20, #0x37f",
|
|
"strh w20, [x28, #1200]",
|
|
"strb wzr, [x28, #1051]",
|
|
"strb wzr, [x28, #1202]",
|
|
"strb wzr, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb wzr, [x28, #1050]",
|
|
"strb wzr, [x28, #1054]",
|
|
"strb wzr, [x28, #1040]"
|
|
]
|
|
},
|
|
"fnstsw [rax]": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xdd !11b /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"lsl x20, x20, #11",
|
|
"ldrb w21, [x28, #1048]",
|
|
"orr x20, x20, x21, lsl #8",
|
|
"ldrb w21, [x28, #1049]",
|
|
"orr x20, x20, x21, lsl #9",
|
|
"ldrb w21, [x28, #1050]",
|
|
"orr x20, x20, x21, lsl #10",
|
|
"ldrb w21, [x28, #1054]",
|
|
"orr x20, x20, x21, lsl #14",
|
|
"ldrb w21, [x28, #1040]",
|
|
"orr x20, x20, x21",
|
|
"strh w20, [x4]"
|
|
]
|
|
},
|
|
"ffree st0": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xdd 11b 0xc0 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"ffree st1": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xdd 11b 0xc1 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"ffree st2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xdd 11b 0xc2 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"ffree st3": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xdd 11b 0xc3 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x3 (3)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"ffree st4": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xdd 11b 0xc4 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"ffree st5": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xdd 11b 0xc5 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"ffree st6": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xdd 11b 0xc6 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"ffree st7": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xdd 11b 0xc7 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fst st0": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Comment": [
|
|
"0xdd 11b 0xd0 /2"
|
|
],
|
|
"ExpectedArm64ASM": []
|
|
},
|
|
"fst st1": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xdd 11b 0xd1 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fst st2": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xdd 11b 0xd2 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fst st3": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xdd 11b 0xd3 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x3 (3)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fst st4": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xdd 11b 0xd4 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fst st5": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xdd 11b 0xd5 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fst st6": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xdd 11b 0xd6 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fst st7": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xdd 11b 0xd7 /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fstp st0": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xdd 11b 0xd8 /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fstp st1": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xdd 11b 0xd9 /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"add x22, x28, x21, lsl #4",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w22, [x28, #1202]",
|
|
"mov w23, #0x1",
|
|
"lsl w21, w23, w21",
|
|
"orr w21, w22, w21",
|
|
"lsl w20, w23, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fstp st2": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xdd 11b 0xda /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"add w21, w21, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w22, [x28, #1202]",
|
|
"mov w23, #0x1",
|
|
"lsl w21, w23, w21",
|
|
"orr w21, w22, w21",
|
|
"lsl w20, w23, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fstp st3": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xdd 11b 0xdb /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"add w21, w21, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w22, [x28, #1202]",
|
|
"mov w23, #0x1",
|
|
"lsl w21, w23, w21",
|
|
"orr w21, w22, w21",
|
|
"lsl w20, w23, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fstp st4": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xdd 11b 0xdc /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"add w21, w21, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w22, [x28, #1202]",
|
|
"mov w23, #0x1",
|
|
"lsl w21, w23, w21",
|
|
"orr w21, w22, w21",
|
|
"lsl w20, w23, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fstp st5": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xdd 11b 0xdd /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"add w21, w21, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w22, [x28, #1202]",
|
|
"mov w23, #0x1",
|
|
"lsl w21, w23, w21",
|
|
"orr w21, w22, w21",
|
|
"lsl w20, w23, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fstp st6": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xdd 11b 0xde /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"add w21, w21, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w22, [x28, #1202]",
|
|
"mov w23, #0x1",
|
|
"lsl w21, w23, w21",
|
|
"orr w21, w22, w21",
|
|
"lsl w20, w23, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fstp st7": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xdd 11b 0xdf /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"add w21, w21, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w22, [x28, #1202]",
|
|
"mov w23, #0x1",
|
|
"lsl w21, w23, w21",
|
|
"orr w21, w22, w21",
|
|
"lsl w20, w23, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucom st0": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xdd 11b 0xe0 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"mrs x20, nzcv",
|
|
"fcmp d2, d2",
|
|
"cset x21, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w21",
|
|
"orr w23, w23, w21",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w21, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"fucom st1": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdd 11b 0xe1 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fucom st2": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdd 11b 0xe2 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fucom st3": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdd 11b 0xe3 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fucom st4": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdd 11b 0xe4 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fucom st5": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdd 11b 0xe5 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fucom st6": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdd 11b 0xe6 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fucom st7": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdd 11b 0xe7 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w20",
|
|
"orr w23, w23, w20",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"fucomp st0": {
|
|
"ExpectedInstructionCount": 23,
|
|
"Comment": [
|
|
"0xdd 11b 0xe8 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"fcmp d2, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomp st1": {
|
|
"ExpectedInstructionCount": 25,
|
|
"Comment": [
|
|
"0xdd 11b 0xe9 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"mrs x22, nzcv",
|
|
"add x23, x28, x20, lsl #4",
|
|
"ldr d3, [x23, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x23, vs",
|
|
"cset x24, lo",
|
|
"cset x30, eq",
|
|
"orr w24, w24, w23",
|
|
"orr w30, w30, w23",
|
|
"strb w24, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w23, [x28, #1050]",
|
|
"strb w30, [x28, #1054]",
|
|
"msr nzcv, x22",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomp st2": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xdd 11b 0xea /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomp st3": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xdd 11b 0xeb /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomp st4": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xdd 11b 0xec /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomp st5": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xdd 11b 0xed /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomp st6": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xdd 11b 0xee /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomp st7": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": [
|
|
"0xdd 11b 0xef /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"mrs x21, nzcv",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x21",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fiadd word [rax]": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xde !11b /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"sxth x20, w20",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fimul word [rax]": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xde !11b /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"sxth x20, w20",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"ficom word [rax]": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": [
|
|
"0xde !11b /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"sxth x20, w20",
|
|
"scvtf d2, w20",
|
|
"mrs x20, nzcv",
|
|
"ldrb w21, [x28, #1051]",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x21, vs",
|
|
"cset x22, lo",
|
|
"cset x23, eq",
|
|
"orr w22, w22, w21",
|
|
"orr w23, w23, w21",
|
|
"strb w22, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w21, [x28, #1050]",
|
|
"strb w23, [x28, #1054]",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ficomp word [rax]": {
|
|
"ExpectedInstructionCount": 26,
|
|
"Comment": [
|
|
"0xde !11b /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"sxth x20, w20",
|
|
"scvtf d2, w20",
|
|
"mrs x20, nzcv",
|
|
"ldrb w21, [x28, #1051]",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x22, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w22",
|
|
"orr w24, w24, w22",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w22, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w22, w21, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"msr nzcv, x20",
|
|
"strb w22, [x28, #1051]",
|
|
"ldrb w20, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w21, w22, w21",
|
|
"bic w20, w20, w21",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fisub word [rax]": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xde !11b /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"sxth x20, w20",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fisubr word [rax]": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xde !11b /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"sxth x20, w20",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fsub d2, d2, d3",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fidiv word [rax]": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xde !11b /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"sxth x20, w20",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"fidivr word [rax]": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0xde !11b /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"sxth x20, w20",
|
|
"scvtf d2, w20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fdiv d2, d2, d3",
|
|
"str d2, [x20, #1056]"
|
|
]
|
|
},
|
|
"faddp st0": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xd8 11b 0xc0 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fadd d2, d2, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"faddp st1": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xde 11b 0xc1 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"faddp st2": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xc2 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"faddp st3": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xc3 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"faddp st4": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xc4 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"faddp st5": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xc5 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"faddp st6": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xc6 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"faddp st7": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xc7 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fadd d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fmulp st0": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xde 11b 0xc8 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fmul d2, d2, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fmulp st1": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xde 11b 0xc9 /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fmulp st2": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xca /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fmulp st3": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xcb /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fmulp st4": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xcc /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fmulp st5": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xcd /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fmulp st6": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xce /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fmulp st7": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xcf /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fmul d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcompp": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": [
|
|
"0xde 11b 0xd9 /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"mrs x22, nzcv",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d3, [x20, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x20, vs",
|
|
"cset x23, lo",
|
|
"cset x24, eq",
|
|
"orr w23, w23, w20",
|
|
"orr w24, w24, w20",
|
|
"strb w23, [x28, #1048]",
|
|
"strb wzr, [x28, #1049]",
|
|
"strb w20, [x28, #1050]",
|
|
"strb w24, [x28, #1054]",
|
|
"add w20, w21, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"msr nzcv, x22",
|
|
"strb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x8",
|
|
"sub w20, w22, w20",
|
|
"mov w22, #0xc0c0",
|
|
"lsr w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"db 0xde, 0xe0": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"fsubrp st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xde 11b 0xe0 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fsub d2, d2, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubrp st1, st0": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xde 11b 0xe1 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"add x23, x28, x20, lsl #4",
|
|
"ldr d3, [x23, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubrp st2, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xe2 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubrp st3, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xe3 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubrp st4, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xe4 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubrp st5, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xe5 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubrp st6, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xe6 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubrp st7, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xe7 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"db 0xde, 0xe8": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"fsubp st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xde 11b 0xe8 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fsub d2, d2, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubp st1, st0": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xde 11b 0xe9 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubp st2, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xea /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubp st3, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xeb /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubp st4, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xec /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubp st5, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xed /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubp st6, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xee /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fsubp st7, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xef /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fsub d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"db 0xde, 0xf0": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"fdivrp st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xde 11b 0xf0 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fdiv d2, d2, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivrp st1, st0": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xde 11b 0xf1 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"add x23, x28, x20, lsl #4",
|
|
"ldr d3, [x23, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivrp st2, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xf2 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivrp st3, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xf3 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivrp st4, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xf4 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivrp st5, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xf5 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivrp st6, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xf6 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivrp st7, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xf7 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"db 0xde, 0xf8": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"fdivp st0, st0",
|
|
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
|
|
"0xde 11b 0xf8 /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fdiv d2, d2, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivp st1, st0": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xde 11b 0xf9 /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x22, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivp st2, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xfa /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivp st3, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xfb /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivp st4, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xfc /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivp st5, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xfd /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivp st6, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xfe /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fdivp st7, st0": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xde 11b 0xff /7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fdiv d2, d3, d2",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"strb w22, [x28, #1051]",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fild word [rax]": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdf !11b /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"sxth x20, w20",
|
|
"scvtf d2, x20",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fisttp word [rax]": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xdf !11b /1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fcvtzs x21, d2",
|
|
"strh w21, [x4]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fist word [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xdf !11b /2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"ldr d2, [x20, #1056]",
|
|
"frinti d0, d2",
|
|
"fcvtzs x20, d0",
|
|
"strh w20, [x4]"
|
|
]
|
|
},
|
|
"fistp word [rax]": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xdf !11b /3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"frinti d0, d2",
|
|
"fcvtzs x21, d0",
|
|
"strh w21, [x4]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fbld tword [rax]": {
|
|
"ExpectedInstructionCount": 28,
|
|
"Comment": [
|
|
"0xdf !11b /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"add x20, x4, #0x8 (8)",
|
|
"ld1 {v2.h}[4], [x20]",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v2.16b",
|
|
"ldr x0, [x28, #2008]",
|
|
"ldr x3, [x28, #2016]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v2.16b",
|
|
"ldr x0, [x28, #1688]",
|
|
"ldr x3, [x28, #1696]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"fmov d2, d0",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"orr w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fbstp tword [rax]": {
|
|
"ExpectedInstructionCount": 28,
|
|
"Comment": [
|
|
"0xdf !11b /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"str x30, [sp, #-16]!",
|
|
"fmov d0, d2",
|
|
"ldr x0, [x28, #1656]",
|
|
"ldr x3, [x28, #1664]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"str x30, [sp, #-16]!",
|
|
"mov v0.16b, v2.16b",
|
|
"ldr x0, [x28, #1992]",
|
|
"ldr x3, [x28, #2000]",
|
|
"blr x0",
|
|
"ldr x30, [sp], #16",
|
|
"mov v2.16b, v0.16b",
|
|
"str d2, [x4]",
|
|
"mov x21, v2.d[1]",
|
|
"strh w21, [x4, #8]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"ffreep st0": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xdf 11b 0xc0 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"ffreep st1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xdf 11b 0xc1 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"ffreep st2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xdf 11b 0xc2 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"ffreep st3": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xdf 11b 0xc3 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"ffreep st4": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xdf 11b 0xc4 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"ffreep st5": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xdf 11b 0xc5 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"ffreep st6": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xdf 11b 0xc6 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"ffreep st7": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xdf 11b 0xc7 /0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]"
|
|
]
|
|
},
|
|
"fnstsw ax": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xdf 11b 0xe0 /4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"lsl x20, x20, #11",
|
|
"ldrb w21, [x28, #1048]",
|
|
"orr x20, x20, x21, lsl #8",
|
|
"ldrb w21, [x28, #1049]",
|
|
"orr x20, x20, x21, lsl #9",
|
|
"ldrb w21, [x28, #1050]",
|
|
"orr x20, x20, x21, lsl #10",
|
|
"ldrb w21, [x28, #1054]",
|
|
"orr x20, x20, x21, lsl #14",
|
|
"ldrb w21, [x28, #1040]",
|
|
"orr x20, x20, x21",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"fucomip st0": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xdf 11b 0xe8 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fcmp d2, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomip st1": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xdf 11b 0xe9 /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomip st2": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xea /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomip st3": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xeb /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomip st4": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xec /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomip st5": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xed /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomip st6": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xee /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fucomip st7": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xef /5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomip st0": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0xdf 11b 0xf0 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"fcmp d2, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomip st1": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0xdf 11b 0xf1 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d2, [x22, #1056]",
|
|
"add x22, x28, x20, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomip st2": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xf2 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomip st3": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xf3 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomip st4": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xf4 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x4 (4)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomip st5": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xf5 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x5 (5)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomip st6": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xf6 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x6 (6)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"fcomip st7": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": [
|
|
"0xdf 11b 0xf7 /6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w21, w20, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"fcmp d3, d2",
|
|
"cset x26, vc",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"memcpy4_32": {
|
|
"x86InstructionCount": 8,
|
|
"ExpectedInstructionCount": 16,
|
|
"x86Insts": [
|
|
"fld dword [rax]",
|
|
"fstp dword [rdx]",
|
|
"fld dword [rax + 4]",
|
|
"fstp dword [rdx + 4]",
|
|
"fld dword [rax + 8]",
|
|
"fstp dword [rdx + 8]",
|
|
"fld dword [rax + 12]",
|
|
"fstp dword [rdx + 12]"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"str s2, [x5]",
|
|
"ldr s2, [x4, #4]",
|
|
"str s2, [x5, #4]",
|
|
"ldr s2, [x4, #8]",
|
|
"str s2, [x5, #8]",
|
|
"ldr s2, [x4, #12]",
|
|
"str s2, [x5, #12]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"memcpy4_64": {
|
|
"x86InstructionCount": 8,
|
|
"ExpectedInstructionCount": 16,
|
|
"x86Insts": [
|
|
"fld qword [rax]",
|
|
"fstp qword [rdx]",
|
|
"fld qword [rax + 8]",
|
|
"fstp qword [rdx + 8]",
|
|
"fld qword [rax + 16]",
|
|
"fstp qword [rdx + 16]",
|
|
"fld qword [rax + 32]",
|
|
"fstp qword [rdx + 32]"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"str d2, [x5]",
|
|
"ldr d2, [x4, #8]",
|
|
"str d2, [x5, #8]",
|
|
"ldr d2, [x4, #16]",
|
|
"str d2, [x5, #16]",
|
|
"ldr d2, [x4, #32]",
|
|
"str d2, [x5, #32]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"Multiple fld/fst": {
|
|
"x86InstructionCount": 4,
|
|
"ExpectedInstructionCount": 22,
|
|
"x86Insts": [
|
|
"fld qword [ebp+16380]",
|
|
"fstp qword [eax-0x4]",
|
|
"fld qword [ebp-0x8]",
|
|
"fstp qword [eax+16370]"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3ffc",
|
|
"add x20, x9, x20",
|
|
"mov w20, w20",
|
|
"ldr d2, [x20]",
|
|
"sub x20, x4, #0x4 (4)",
|
|
"mov w20, w20",
|
|
"str d2, [x20]",
|
|
"sub x20, x9, #0x8 (8)",
|
|
"mov w20, w20",
|
|
"ldr d2, [x20]",
|
|
"mov w20, #0x3ff2",
|
|
"add x20, x4, x20",
|
|
"mov w20, w20",
|
|
"str d2, [x20]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"memcpy4_80": {
|
|
"x86InstructionCount": 8,
|
|
"ExpectedInstructionCount": 38,
|
|
"x86Insts": [
|
|
"fld tword [rax]",
|
|
"fstp tword [rdx]",
|
|
"fld tword [rax + 10]",
|
|
"fstp tword [rdx + 10]",
|
|
"fld tword [rax + 20]",
|
|
"fstp tword [rdx + 20]",
|
|
"fld tword [rax + 30]",
|
|
"fstp tword [rdx + 30]"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"add x20, x4, #0x8 (8)",
|
|
"ld1 {v2.h}[4], [x20]",
|
|
"str d2, [x5]",
|
|
"mov x20, v2.d[1]",
|
|
"strh w20, [x5, #8]",
|
|
"add x20, x4, #0xa (10)",
|
|
"ldr d2, [x20]",
|
|
"add x20, x20, #0x8 (8)",
|
|
"ld1 {v2.h}[4], [x20]",
|
|
"stur d2, [x5, #10]",
|
|
"mov x20, v2.d[1]",
|
|
"add x21, x5, #0xa (10)",
|
|
"strh w20, [x21, #8]",
|
|
"add x20, x4, #0x14 (20)",
|
|
"ldr d2, [x20]",
|
|
"add x20, x20, #0x8 (8)",
|
|
"ld1 {v2.h}[4], [x20]",
|
|
"stur d2, [x5, #20]",
|
|
"mov x20, v2.d[1]",
|
|
"add x21, x5, #0x14 (20)",
|
|
"strh w20, [x21, #8]",
|
|
"add x20, x4, #0x1e (30)",
|
|
"ldr d2, [x20]",
|
|
"add x20, x20, #0x8 (8)",
|
|
"ld1 {v2.h}[4], [x20]",
|
|
"stur d2, [x5, #30]",
|
|
"mov x20, v2.d[1]",
|
|
"add x21, x5, #0x1e (30)",
|
|
"strh w20, [x21, #8]",
|
|
"ldrb w20, [x28, #1051]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
}
|
|
}
|
|
}
|