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Ryan Houdek
b275068569
The AMD documentation about this instruction is very vague and misleading in multiple ways. While the Intel documentation is much cleaner and explains how we need to implement these. 8 of these "new" operations are just inverted signaling versions of the original 8 SSE versions. The remaining 16 new operations fill gaps in the original x86 version of the instructions, exposing the 5 bit truth tables directly, which is why we also have a "true" and "false" version as well. Both scalar and vector wide. Fixes #5326