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FEX-Emu--FEX/unittests/InstructionCountCI/SecondaryGroup.json
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Alyssa Rosenzweig 3383786205 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-08-10 15:21:08 -04:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"RNG"
],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"AFP",
"FLAGM",
"FLAGM2"
]
},
"Instructions": {
"sgdt [rax]": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP7 0x0F 0x1 /0",
"ExpectedArm64ASM": [
"mov w20, #0x0",
"strh w20, [x4]",
"mov x20, #0xfffffffffffe0000",
"stur x20, [x4, #2]"
]
},
"bt ax, 0": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt eax, 0": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt rax, 0": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt ax, 15": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"eor x20, x4, #0x8000",
"ubfx x20, x20, #15, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt eax, 31": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"eor x20, x4, #0x80000000",
"ubfx x20, x20, #31, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt rax, 63": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"eor x20, x4, #0x8000000000000000",
"lsr x20, x20, #63",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt word [rax], 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt dword [rax], 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt qword [rax], 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt word [rax], 15": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt dword [rax], 31": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt qword [rax], 63": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts ax, 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"orr w21, w4, #0x1",
"bfxil x4, x21, #0, #16",
"msr nzcv, x20"
]
},
"bts eax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"orr w4, w4, #0x1",
"msr nzcv, x20"
]
},
"bts rax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"orr x4, x4, #0x1",
"msr nzcv, x20"
]
},
"bts ax, 15": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"eor x20, x4, #0x8000",
"ubfx x20, x20, #15, #1",
"lsl x20, x20, #29",
"orr w21, w4, #0x8000",
"bfxil x4, x21, #0, #16",
"msr nzcv, x20"
]
},
"bts eax, 31": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"eor x20, x4, #0x80000000",
"ubfx x20, x20, #31, #1",
"lsl x20, x20, #29",
"orr w4, w4, #0x80000000",
"msr nzcv, x20"
]
},
"bts rax, 63": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"eor x20, x4, #0x8000000000000000",
"lsr x20, x20, #63",
"lsl x20, x20, #29",
"orr x4, x4, #0x8000000000000000",
"msr nzcv, x20"
]
},
"bts word [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"orr x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts dword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"orr x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts qword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"orr x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts word [rax], 15": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"orr x21, x20, #0x80",
"strb w21, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts dword [rax], 31": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"orr x21, x20, #0x80",
"strb w21, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts qword [rax], 63": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"orr x21, x20, #0x80",
"strb w21, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock bts word [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldsetalb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock bts dword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldsetalb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock bts qword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldsetalb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock bts word [rax], 15": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x1 (1)",
"ldsetalb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock bts dword [rax], 31": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x3 (3)",
"ldsetalb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock bts qword [rax], 63": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x7 (7)",
"ldsetalb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr ax, 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"and w21, w4, #0xfffffffe",
"bfxil x4, x21, #0, #16",
"msr nzcv, x20"
]
},
"btr eax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"and w4, w4, #0xfffffffe",
"msr nzcv, x20"
]
},
"btr rax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"and x4, x4, #0xfffffffffffffffe",
"msr nzcv, x20"
]
},
"btr ax, 15": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"eor x20, x4, #0x8000",
"ubfx x20, x20, #15, #1",
"lsl x20, x20, #29",
"and w21, w4, #0xffff7fff",
"bfxil x4, x21, #0, #16",
"msr nzcv, x20"
]
},
"btr eax, 31": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"eor x20, x4, #0x80000000",
"ubfx x20, x20, #31, #1",
"lsl x20, x20, #29",
"and w4, w4, #0x7fffffff",
"msr nzcv, x20"
]
},
"btr rax, 63": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"eor x20, x4, #0x8000000000000000",
"lsr x20, x20, #63",
"lsl x20, x20, #29",
"and x4, x4, #0x7fffffffffffffff",
"msr nzcv, x20"
]
},
"btr word [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"and x21, x20, #0xfffffffffffffffe",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr dword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"and x21, x20, #0xfffffffffffffffe",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr qword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"and x21, x20, #0xfffffffffffffffe",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr word [rax], 15": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"and x21, x20, #0xffffffffffffff7f",
"strb w21, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr dword [rax], 31": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"and x21, x20, #0xffffffffffffff7f",
"strb w21, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr qword [rax], 63": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"and x21, x20, #0xffffffffffffff7f",
"strb w21, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btr word [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldclralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btr dword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldclralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btr qword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldclralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btr word [rax], 15": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x1 (1)",
"ldclralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btr dword [rax], 31": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x3 (3)",
"ldclralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btr qword [rax], 63": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x7 (7)",
"ldclralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc ax, 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"eor w21, w4, #0x1",
"bfxil x4, x21, #0, #16",
"msr nzcv, x20"
]
},
"btc eax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"eor w4, w4, #0x1",
"msr nzcv, x20"
]
},
"btc rax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor x20, x4, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"eor x4, x4, #0x1",
"msr nzcv, x20"
]
},
"btc ax, 15": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor x20, x4, #0x8000",
"ubfx x20, x20, #15, #1",
"lsl x20, x20, #29",
"eor w21, w4, #0x8000",
"bfxil x4, x21, #0, #16",
"msr nzcv, x20"
]
},
"btc eax, 31": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor x20, x4, #0x80000000",
"ubfx x20, x20, #31, #1",
"lsl x20, x20, #29",
"eor w4, w4, #0x80000000",
"msr nzcv, x20"
]
},
"btc rax, 63": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor x20, x4, #0x8000000000000000",
"lsr x20, x20, #63",
"lsl x20, x20, #29",
"eor x4, x4, #0x8000000000000000",
"msr nzcv, x20"
]
},
"btc word [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc dword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc qword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc word [rax], 15": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"eor x21, x20, #0x80",
"strb w21, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc dword [rax], 31": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"eor x21, x20, #0x80",
"strb w21, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc qword [rax], 63": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"eor x21, x20, #0x80",
"strb w21, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btc word [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldeoralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btc dword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldeoralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btc qword [rax], 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldeoralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btc word [rax], 15": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x1 (1)",
"ldeoralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btc dword [rax], 31": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x3 (3)",
"ldeoralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btc qword [rax], 63": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x7 (7)",
"ldeoralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"cmpxchg8b [rbp]": {
"ExpectedInstructionCount": 23,
"Comment": "GROUP9 0x0F 0xC7 /1",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w6",
"mov w20, w20",
"mov w21, w21",
"mov w22, w7",
"mov w23, w5",
"mov w22, w22",
"mov w23, w23",
"mov w2, w20",
"mov w3, w21",
"caspal w2, w3, w22, w23, [x9]",
"mov w22, w2",
"mov w23, w3",
"mrs x0, nzcv",
"cmp w22, w20",
"ccmp w23, w21, #nzcv, eq",
"cset w1, eq",
"bfi w0, w1, #30, #1",
"msr nzcv, x0",
"mov w20, w23",
"mov w21, w22",
"csel x4, x21, x4, ne",
"csel x6, x20, x6, ne"
]
},
"cmpxchg16b [rbp]": {
"ExpectedInstructionCount": 19,
"Comment": "GROUP9 0x0F 0xC7 /1",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x6",
"mov x22, x7",
"mov x23, x5",
"mov x2, x20",
"mov x3, x21",
"caspal x2, x3, x22, x23, [x9]",
"mov x22, x2",
"mov x23, x3",
"mrs x0, nzcv",
"cmp w22, w20",
"ccmp w23, w21, #nzcv, eq",
"cset w1, eq",
"bfi w0, w1, #30, #1",
"msr nzcv, x0",
"mov x20, x23",
"mov x21, x22",
"csel x4, x21, x4, ne",
"csel x6, x20, x6, ne"
]
},
"rdrand ax": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"bfxil x4, x20, #0, #16",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand eax": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"mov w4, w20",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand rax": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x4, rndr",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed ax": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"bfxil x4, x20, #0, #16",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed eax": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"mov w4, w20",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed rax": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x4, rndrrs",
"mov w26, #0x1",
"mov w27, #0x0",
"cset w20, eq",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdpid eax": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"str x8, [x28, #312]",
"mov w0, #0x100",
"str x0, [x28, #1312]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
"add x1, sp, #0x4 (4)",
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #1000]",
"msr nzcv, x8",
"ldr x8, [x28, #312]",
"str xzr, [x28, #1312]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
},
"rdpid rax": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"str x8, [x28, #312]",
"mov w0, #0x100",
"str x0, [x28, #1312]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
"add x1, sp, #0x4 (4)",
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #1000]",
"msr nzcv, x8",
"ldr x8, [x28, #312]",
"str xzr, [x28, #1312]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
},
"psrlw mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrlw mm0, 15": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #1040]"
]
},
"psrlw mm0, 16": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]"
]
},
"psrlw xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrlw xmm0, 15": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ushr v16.8h, v16.8h, #15"
]
},
"psrlw xmm0, 16": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psraw mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psraw mm0, 15": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #1040]"
]
},
"psraw mm0, 16": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #1040]"
]
},
"psraw xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psraw xmm0, 15": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"sshr v16.8h, v16.8h, #15"
]
},
"psraw xmm0, 16": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"sshr v16.8h, v16.8h, #15"
]
},
"psllw mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"psllw mm0, 15": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #1040]"
]
},
"psllw mm0, 16": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]"
]
},
"psllw xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"psllw xmm0, 15": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"shl v16.8h, v16.8h, #15"
]
},
"psllw xmm0, 16": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psrld mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrld mm0, 31": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #1040]"
]
},
"psrld mm0, 32": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]"
]
},
"psrld xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrld xmm0, 31": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ushr v16.4s, v16.4s, #31"
]
},
"psrld xmm0, 32": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psrad mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psrad mm0, 31": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #1040]"
]
},
"psrad mm0, 32": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #1040]"
]
},
"psrad xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psrad xmm0, 31": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"sshr v16.4s, v16.4s, #31"
]
},
"psrad xmm0, 32": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"sshr v16.4s, v16.4s, #31"
]
},
"pslld mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"pslld mm0, 31": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #1040]"
]
},
"pslld mm0, 32": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]"
]
},
"pslld xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"pslld xmm0, 31": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"shl v16.4s, v16.4s, #31"
]
},
"pslld xmm0, 32": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psrlq mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrlq mm0, 63": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #1040]"
]
},
"psrlq mm0, 64": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]"
]
},
"psrlq xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrlq xmm0, 63": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ushr v16.2d, v16.2d, #63"
]
},
"psrlq xmm0, 64": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psrldq xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psrldq xmm0, 15": {
"ExpectedInstructionCount": 2,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ext v16.16b, v16.16b, v2.16b, #15"
]
},
"psrldq xmm0, 16": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psllq mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"psllq mm0, 63": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #1040]"
]
},
"psllq mm0, 64": {
"ExpectedInstructionCount": 3,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]"
]
},
"psllq xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"psllq xmm0, 63": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"shl v16.2d, v16.2d, #63"
]
},
"psllq xmm0, 64": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"fxsave [rax]": {
"ExpectedInstructionCount": 52,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1296]",
"strh w20, [x4]",
"ldrb w20, [x28, #1019]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1016]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1017]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1018]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1022]",
"orr x20, x20, x21, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
"str q18, [x4, #192]",
"str q19, [x4, #208]",
"str q20, [x4, #224]",
"str q21, [x4, #240]",
"str q22, [x4, #256]",
"str q23, [x4, #272]",
"str q24, [x4, #288]",
"str q25, [x4, #304]",
"str q26, [x4, #320]",
"str q27, [x4, #336]",
"str q28, [x4, #352]",
"str q29, [x4, #368]",
"str q30, [x4, #384]",
"str q31, [x4, #400]",
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4, #24]",
"mov w20, #0xffff",
"str w20, [x4, #28]"
]
},
"rdfsbase eax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr w4, [x28, #968]"
]
},
"rdfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr x4, [x28, #968]"
]
},
"fxrstor [rax]": {
"ExpectedInstructionCount": 58,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1296]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1019]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w20, w20, #14, #1",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"ldr q2, [x4, #32]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
"ldr q19, [x4, #208]",
"ldr q20, [x4, #224]",
"ldr q21, [x4, #240]",
"ldr q22, [x4, #256]",
"ldr q23, [x4, #272]",
"ldr q24, [x4, #288]",
"ldr q25, [x4, #304]",
"ldr q26, [x4, #320]",
"ldr q27, [x4, #336]",
"ldr q28, [x4, #352]",
"ldr q29, [x4, #368]",
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"ldr w21, [x4, #24]",
"and w21, w21, #0xffc0",
"str w21, [x28, #940]",
"ubfx w22, w21, #13, #3",
"rbit w1, w22",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x22, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"strb w20, [x28, #1298]",
"str q9, [x28, #1152]",
"str q8, [x28, #1136]",
"str q7, [x28, #1120]",
"str q6, [x28, #1104]",
"str q5, [x28, #1088]",
"str q4, [x28, #1072]",
"str q3, [x28, #1056]",
"str q2, [x28, #1040]"
]
},
"rdgsbase eax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr w4, [x28, #960]"
]
},
"rdgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr x4, [x28, #960]"
]
},
"ldmxcsr [rax]": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0"
]
},
"wrfsbase eax": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #968]"
]
},
"wrfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"str x4, [x28, #968]"
]
},
"stmxcsr [rax]": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4]"
]
},
"wrgsbase eax": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #960]"
]
},
"wrgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"str x4, [x28, #960]"
]
},
"xsave [rax]": {
"ExpectedInstructionCount": 98,
"Comment": "GROUP15 0x0F 0xAE /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"cbnz x20, #+0x8",
"b #+0x80",
"ldrh w20, [x28, #1296]",
"strh w20, [x4]",
"ldrb w20, [x28, #1019]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1016]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1017]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1018]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1022]",
"orr x20, x20, x21, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
"b #+0x44",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
"str q18, [x4, #192]",
"str q19, [x4, #208]",
"str q20, [x4, #224]",
"str q21, [x4, #240]",
"str q22, [x4, #256]",
"str q23, [x4, #272]",
"str q24, [x4, #288]",
"str q25, [x4, #304]",
"str q26, [x4, #320]",
"str q27, [x4, #336]",
"str q28, [x4, #352]",
"str q29, [x4, #368]",
"str q30, [x4, #384]",
"str q31, [x4, #400]",
"ubfx x20, x4, #2, #1",
"cbnz x20, #+0x8",
"b #+0x84",
"ldr q2, [x28, #16]",
"str q2, [x4, #576]",
"ldr q2, [x28, #32]",
"str q2, [x4, #592]",
"ldr q2, [x28, #48]",
"str q2, [x4, #608]",
"ldr q2, [x28, #64]",
"str q2, [x4, #624]",
"ldr q2, [x28, #80]",
"str q2, [x4, #640]",
"ldr q2, [x28, #96]",
"str q2, [x4, #656]",
"ldr q2, [x28, #112]",
"str q2, [x4, #672]",
"ldr q2, [x28, #128]",
"str q2, [x4, #688]",
"ldr q2, [x28, #144]",
"str q2, [x4, #704]",
"ldr q2, [x28, #160]",
"str q2, [x4, #720]",
"ldr q2, [x28, #176]",
"str q2, [x4, #736]",
"ldr q2, [x28, #192]",
"str q2, [x4, #752]",
"ldr q2, [x28, #208]",
"str q2, [x4, #768]",
"ldr q2, [x28, #224]",
"str q2, [x4, #784]",
"ldr q2, [x28, #240]",
"str q2, [x4, #800]",
"ldr q2, [x28, #256]",
"str q2, [x4, #816]",
"ubfx x20, x4, #1, #2",
"cbnz x20, #+0x8",
"b #+0x18",
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4, #24]",
"mov w20, #0xffff",
"str w20, [x4, #28]",
"ubfx x20, x4, #0, #3",
"str x20, [x4, #512]"
]
},
"lfence": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"dmb ld"
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 166,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"sub sp, sp, #0x40 (64)",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #0, #1",
"cbnz x20, #+0x8",
"b #+0x84",
"ldrh w20, [x4]",
"strh w20, [x28, #1296]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1019]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w20, w20, #14, #1",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"ldr q2, [x4, #32]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"strb w20, [x28, #1298]",
"str q9, [x28, #1152]",
"str q8, [x28, #1136]",
"str q7, [x28, #1120]",
"str q6, [x28, #1104]",
"str q5, [x28, #1088]",
"str q4, [x28, #1072]",
"str q3, [x28, #1056]",
"str q2, [x28, #1040]",
"b #+0x48",
"mov w20, #0x37f",
"strh w20, [x28, #1296]",
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1016]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1018]",
"strb wzr, [x28, #1022]",
"movi v2.2d, #0x0",
"strb wzr, [x28, #1298]",
"str q2, [x28, #1152]",
"str q2, [x28, #1136]",
"str q2, [x28, #1120]",
"str q2, [x28, #1104]",
"str q2, [x28, #1088]",
"str q2, [x28, #1072]",
"str q2, [x28, #1056]",
"str q2, [x28, #1040]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",
"b #+0x48",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
"ldr q19, [x4, #208]",
"ldr q20, [x4, #224]",
"ldr q21, [x4, #240]",
"ldr q22, [x4, #256]",
"ldr q23, [x4, #272]",
"ldr q24, [x4, #288]",
"ldr q25, [x4, #304]",
"ldr q26, [x4, #320]",
"ldr q27, [x4, #336]",
"ldr q28, [x4, #352]",
"ldr q29, [x4, #368]",
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"b #+0x44",
"movi v31.2d, #0x0",
"mov v30.16b, v31.16b",
"mov v29.16b, v31.16b",
"mov v28.16b, v31.16b",
"mov v27.16b, v31.16b",
"mov v26.16b, v31.16b",
"mov v25.16b, v31.16b",
"mov v24.16b, v31.16b",
"mov v23.16b, v31.16b",
"mov v22.16b, v31.16b",
"mov v21.16b, v31.16b",
"mov v20.16b, v31.16b",
"mov v19.16b, v31.16b",
"mov v18.16b, v31.16b",
"mov v17.16b, v31.16b",
"mov v16.16b, v31.16b",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #2, #1",
"cbnz x20, #+0x8",
"b #+0x98",
"ldr q2, [x4, #576]",
"ldr q3, [x4, #592]",
"ldr q4, [x4, #608]",
"ldr q5, [x4, #624]",
"ldr q6, [x4, #640]",
"ldr q7, [x4, #656]",
"ldr q8, [x4, #672]",
"ldr q9, [x4, #688]",
"ldr q10, [x4, #704]",
"ldr q11, [x4, #720]",
"ldr q12, [x4, #736]",
"ldr q13, [x4, #752]",
"ldr q14, [x4, #768]",
"ldr q15, [x4, #784]",
"str q2, [sp]",
"ldr q2, [x4, #800]",
"str q3, [sp, #32]",
"ldr q3, [x4, #816]",
"str q3, [x28, #256]",
"str q2, [x28, #240]",
"str q15, [x28, #224]",
"str q14, [x28, #208]",
"str q13, [x28, #192]",
"str q12, [x28, #176]",
"str q11, [x28, #160]",
"str q10, [x28, #144]",
"str q9, [x28, #128]",
"str q8, [x28, #112]",
"str q7, [x28, #96]",
"str q6, [x28, #80]",
"str q5, [x28, #64]",
"str q4, [x28, #48]",
"ldr q2, [sp, #32]",
"str q2, [x28, #32]",
"ldr q2, [sp]",
"str q2, [x28, #16]",
"b #+0x48",
"movi v2.2d, #0x0",
"str q2, [x28, #256]",
"str q2, [x28, #240]",
"str q2, [x28, #224]",
"str q2, [x28, #208]",
"str q2, [x28, #192]",
"str q2, [x28, #176]",
"str q2, [x28, #160]",
"str q2, [x28, #144]",
"str q2, [x28, #128]",
"str q2, [x28, #112]",
"str q2, [x28, #96]",
"str q2, [x28, #80]",
"str q2, [x28, #64]",
"str q2, [x28, #48]",
"str q2, [x28, #32]",
"str q2, [x28, #16]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #2",
"cbnz x20, #+0x8",
"b #+0x34",
"ldr w20, [x4, #24]",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"b #+0x4",
"add sp, sp, #0x40 (64)"
]
},
"mfence": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /6",
"ExpectedArm64ASM": [
"dmb sy"
]
},
"clwb [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /6",
"ExpectedArm64ASM": [
"dc cvac, x4"
]
},
"sfence": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /7",
"ExpectedArm64ASM": [
"dmb st"
]
},
"clflush [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP15 0x0F 0xAE /7",
"ExpectedArm64ASM": [
"dc civac, x4",
"dsb ish"
]
},
"clflushopt [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /7",
"ExpectedArm64ASM": [
"dc civac, x4"
]
},
"prefetchnta [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUP16 0x0F 0x18 /0"
],
"ExpectedArm64ASM": [
"prfm pldl1strm, [x4]"
]
},
"prefetcht0 [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUP16 0x0F 0x18 /1"
],
"ExpectedArm64ASM": [
"prfm pldl1keep, [x4]"
]
},
"prefetcht1 [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUP16 0x0F 0x18 /2"
],
"ExpectedArm64ASM": [
"prfm pldl2keep, [x4]"
]
},
"prefetcht2 [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUP16 0x0F 0x18 /3"
],
"ExpectedArm64ASM": [
"prfm pldl3keep, [x4]"
]
},
"db 0x0f, 0x18, 0x20;": {
"ExpectedInstructionCount": 0,
"Comment": [
"GROUP16 0x0F 0x18 /4",
"nop dword [rax]",
"NOP implementation"
],
"ExpectedArm64ASM": []
},
"db 0x0f, 0x0d, 0x00": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUPP 0x0F 0x0D /0",
"prefetch_exclusive [rax]"
],
"ExpectedArm64ASM": [
"prfm pldl1keep, [x4]"
]
},
"prefetchw [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUPP 0x0F 0x0D /1"
],
"ExpectedArm64ASM": [
"prfm pstl1keep, [x4]"
]
},
"prefetchwt1 [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUPP 0x0F 0x0D /2"
],
"ExpectedArm64ASM": [
"prfm pstl1keep, [x4]"
]
}
}
}
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