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afdbd9ebdc6021590f3ad4dc4e025cbc3dd1776c
FEX-Emu--FEX/Source/Interface/IR/IR.json
T
Ryan Houdek afdbd9ebdc Fixes issues with PSLLDQ and PSRLDQ 
These are whole vector shift instructions and they shift by bytes rather
than bits.
You only get an immediate offset for the instruction.
Implements two new IR ops to account for these instructions

This also doesn't match AArch64 behaviour 100%, requires two
instructions to emulate rather than the single one on the x86-side
2020-03-06 07:55:59 +02:00

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{
"Defines": [
"constexpr static uint8_t COND_EQ = 0",
"constexpr static uint8_t COND_NEQ = 1",
"constexpr static uint8_t COND_CS = 2",
"constexpr static uint8_t COND_CC = 3",
"constexpr static uint8_t COND_MI = 4",
"constexpr static uint8_t COND_PL = 5",
"constexpr static uint8_t COND_VS = 6",
"constexpr static uint8_t COND_VC = 7",
"constexpr static uint8_t COND_HI = 8",
"constexpr static uint8_t COND_LS = 9",
"constexpr static uint8_t COND_GE = 10",
"constexpr static uint8_t COND_LT = 11",
"constexpr static uint8_t COND_GT = 12",
"constexpr static uint8_t COND_LE = 13"
],
"Ops": {
"Dummy": {
},
"IRHeader": {
"SSAArgs": "1",
"SSANames": [
"Blocks"
],
"Args": [
"uint64_t", "Entry",
"uint32_t", "BlockCount"
]
},
"CodeBlock": {
"SSAArgs": "3",
"RAOverride": "0",
"SSANames": [
"Begin",
"Last",
"Next"
]
},
"BeginBlock": {},
"EndBlock": {
"Args": [
"uint64_t", "RIPIncrement"
]
},
"GuestCallDirect": {
"Args": [
"uint64_t", "RIP",
"uint64_t", "NextRIP"
]
},
"GuestCallIndirect": {
"SSAArgs": "1",
"SSANames": [
"RIP"
],
"Args": [
"uint64_t", "NextRIP"
]
},
"GuestReturn": {
},
"Constant": {
"HasDest": true,
"FixedDestSize": "8",
"Args": [
"uint64_t", "Constant"
]
},
"Break": {
"Args": [
"uint8_t", "Reason",
"uint8_t", "Literal"
]
},
"ExitFunction": {},
"Jump": {
"SSAArgs": "1",
"RAOverride": "0"
},
"CondJump": {
"SSAArgs": "3",
"RAOverride": "1",
"SSANames": [
"Cond",
"TrueBlock",
"FalseBlock"
]
},
"Mov": {
"HasDest": true,
"DestSize": "GetOpSize(ssa0)",
"SSAArgs": "1"
},
"CycleCounter": {
"HasDest": true,
"FixedDestSize": "8"
},
"LoadContext": {
"HasDest": true,
"DestSize": "Size",
"Args": [
"uint8_t", "Size",
"uint32_t", "Offset"
]
},
"StoreContext": {
"SSAArgs": "1",
"Args": [
"uint8_t", "Size",
"uint32_t", "Offset"
]
},
"SpillRegister": {
"SSAArgs": "1",
"Args": [
"uint32_t", "Slot",
"RegisterClassType", "Class"
]
},
"FillRegister": {
"HasDest": true,
"Args": [
"uint32_t", "Slot",
"RegisterClassType", "Class"
]
},
"LoadFlag": {
"HasDest": true,
"DestSize": "1",
"Args": [
"uint32_t", "Flag"
]
},
"StoreFlag": {
"SSAArgs": "1",
"Args": [
"uint32_t", "Flag"
]
},
"Syscall": {
"HasDest": true,
"FixedDestSize": "8",
"SSAArgs": "7"
},
"LoadMem": {
"HasDest": true,
"DestSize": "Size",
"SSAArgs": "1",
"Args": [
"uint8_t", "Size",
"uint8_t", "Align"
]
},
"StoreMem": {
"SSAArgs": "2",
"Args": [
"uint8_t", "Size",
"uint8_t", "Align"
]
},
"Add": {
"HasDest": true,
"SSAArgs": "2"
},
"Sub": {
"HasDest": true,
"SSAArgs": "2"
},
"Mul": {
"HasDest": true,
"SSAArgs": "2"
},
"UMul": {
"HasDest": true,
"SSAArgs": "2"
},
"Div": {
"HasDest": true,
"SSAArgs": "2"
},
"UDiv": {
"HasDest": true,
"SSAArgs": "2"
},
"Rem": {
"HasDest": true,
"SSAArgs": "2"
},
"URem": {
"HasDest": true,
"SSAArgs": "2"
},
"MulH": {
"HasDest": true,
"SSAArgs": "2"
},
"UMulH": {
"HasDest": true,
"SSAArgs": "2"
},
"Or": {
"HasDest": true,
"SSAArgs": "2"
},
"And": {
"HasDest": true,
"SSAArgs": "2"
},
"Xor": {
"HasDest": true,
"SSAArgs": "2"
},
"Lshl": {
"HasDest": true,
"SSAArgs": "2"
},
"Lshr": {
"HasDest": true,
"SSAArgs": "2"
},
"Ashr": {
"HasDest": true,
"SSAArgs": "2"
},
"Rol": {
"HasDest": true,
"SSAArgs": "2"
},
"Ror": {
"HasDest": true,
"SSAArgs": "2"
},
"LDiv": {
"HasDest": true,
"SSAArgs": "3"
},
"LUDiv": {
"HasDest": true,
"SSAArgs": "3"
},
"LRem": {
"HasDest": true,
"SSAArgs": "3"
},
"LURem": {
"HasDest": true,
"SSAArgs": "3"
},
"Zext": {
"HasDest": true,
"DestSize": "SrcSize / 4",
"SSAArgs": "1",
"Args": [
"uint8_t", "SrcSize"
]
},
"Sext": {
"HasDest": true,
"DestSize": "SrcSize / 4",
"SSAArgs": "1",
"Args": [
"uint8_t", "SrcSize"
]
},
"Neg": {
"HasDest": true,
"SSAArgs": "1"
},
"Popcount": {
"HasDest": true,
"SSAArgs": "1"
},
"FindLSB": {
"HasDest": true,
"SSAArgs": "1"
},
"FindMSB": {
"HasDest": true,
"SSAArgs": "1"
},
"Rev": {
"HasDest": true,
"SSAArgs": "1"
},
"CPUID": {
"HasDest": true,
"FixedDestSize": "4",
"NumElements": "4",
"SSAArgs": "1"
},
"Bfi": {
"HasDest": true,
"DestSize": "GetOpSize(ssa0)",
"SSAArgs": "2",
"Args": [
"uint8_t", "Width",
"uint8_t", "lsb"
]
},
"Bfe": {
"HasDest": true,
"DestSize": "GetOpSize(ssa0)",
"SSAArgs": "1",
"Args": [
"uint8_t", "Width",
"uint8_t", "lsb"
]
},
"Sbfe": {
"HasDest": true,
"SSAArgs": "1",
"Args": [
"uint8_t", "Width",
"uint8_t", "lsb"
]
},
"Select": {
"HasDest": true,
"SSAArgs": "4",
"Args": [
"CondClassType", "Cond"
]
},
"CAS": {
"HasDest": true,
"DestSize": "GetOpSize(ssa0)",
"SSAArgs": "3"
},
"Print": {
"SSAArgs": "1"
},
"CreateVector2": {
"HasDest": true,
"DestSize": "GetOpSize(ssa0) * 2",
"SSAArgs": "2"
},
"CreateVector3": {
"HasDest": true,
"DestSize": "GetOpSize(ssa0) * 3",
"SSAArgs": "3"
},
"CreateVector4": {
"HasDest": true,
"DestSize": "GetOpSize(ssa0) * 4",
"SSAArgs": "4"
},
"SplatVector2": {
"HasDest": true,
"NumElements": "2",
"DestSize": "GetOpSize(ssa0) * 2",
"SSAArgs": "1"
},
"SplatVector3": {
"HasDest": true,
"NumElements": "3",
"DestSize": "GetOpSize(ssa0) * 3",
"SSAArgs": "1"
},
"SplatVector4": {
"HasDest": true,
"NumElements": "4",
"DestSize": "GetOpSize(ssa0) * 4",
"SSAArgs": "1"
},
"ExtractElement": {
"HasDest": true,
"DestSize": "GetOpSize(ssa0)",
"SSAArgs": "1",
"Args": [
"uint8_t", "Idx"
]
},
"VOr": {
"HasDest": true,
"SSAArgs": "2"
},
"VXor": {
"HasDest": true,
"SSAArgs": "2"
},
"VAdd": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VSub": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VUMin": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VSMin": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VZip": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VZip2": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VCMPEQ": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VCMPGT": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VUShl": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VUShlS": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VUShr": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize"
]
},
"VInsElement": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize",
"uint8_t", "DestIdx",
"uint8_t", "SrcIdx"
]
},
"VExtr": {
"HasDest": true,
"SSAArgs": "2",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize",
"uint8_t", "Index"
]
},
"VSLI": {
"HasDest": true,
"SSAArgs": "1",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize",
"uint8_t", "ByteShift"
]
},
"VSRI": {
"HasDest": true,
"SSAArgs": "1",
"Args": [
"uint8_t", "RegisterSize",
"uint8_t", "ElementSize",
"uint8_t", "ByteShift"
]
},
"VBitcast": {
"HasDest": true,
"SSAArgs": "1"
},
"Last": {
"Last": true,
"Args": []
}
}
}
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