Ryan Houdek f51832ca6b FEXCore: Fixes a bug with VPSRLDQ/VPSLLDQ with >= 16-byte shifts ...

When the shift amount is >= 16-bytes then we need to zero the register.
We had a bug where we were assigning `Result.High` to itself, which
effectively made the top 128-bits of the ymm register not modify itself.

Adds a unit test to ensure that doesn't happen again.

2024-09-08 15:39:22 -07:00

..

AVX_128.cpp

FEXCore: Fixes a bug with VPSRLDQ/VPSLLDQ with >= 16-byte shifts

2024-09-08 15:39:22 -07:00

Crypto.cpp

OpcodeDispatcher: Fixes PCMUL with weird selectors and zero-extend

2024-06-25 12:54:03 -04:00

Flags.cpp

IR: track whether parity is read

2024-09-07 08:26:04 -04:00

Vector.cpp

AVX128: Fixes 256-bit float compares

2024-08-25 06:33:31 -07:00

X87.cpp

OpcodeDispatcher: defer carry inverts

2024-08-10 13:05:21 -04:00

X87F64.cpp

Fix call to FNINITF64 and refactor

2024-07-26 14:56:06 +02:00