mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 12:00:17 +02:00
4439 lines
111 KiB
JSON
4439 lines
111 KiB
JSON
{
|
|
"Features": {
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"Bitness": 64,
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|
"EnabledHostFeatures": [],
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|
"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"AFP",
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|
"FLAGM",
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|
"FLAGM2"
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|
]
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|
},
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|
"Instructions": {
|
|
"add bl, cl": {
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|
"ExpectedInstructionCount": 5,
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|
"Comment": "0x00",
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|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
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|
"lsl w0, w7, #24",
|
|
"cmn w0, w5, lsl #24",
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|
"add w26, w7, w5",
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|
"bfxil x7, x26, #0, #8"
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]
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|
},
|
|
"add bx, cx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x01",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"lsl w0, w7, #16",
|
|
"cmn w0, w5, lsl #16",
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|
"add w26, w7, w5",
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|
"bfxil x7, x26, #0, #16"
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|
]
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|
},
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|
"add ebx, ecx": {
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|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x01",
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|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"adds w26, w7, w5",
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|
"mov x7, x26"
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|
]
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|
},
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|
"add rbx, rcx": {
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|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x01",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"adds x26, x7, x5",
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|
"mov x7, x26"
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|
]
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},
|
|
"db 0x02, 0xcb": {
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|
"ExpectedInstructionCount": 5,
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|
"Comment": [
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|
"0x02",
|
|
"add bl, cl but modrm.rm as source"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"lsl w0, w5, #24",
|
|
"cmn w0, w7, lsl #24",
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|
"add w26, w5, w7",
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|
"bfxil x5, x26, #0, #8"
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|
]
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},
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|
"db 0x66, 0x03, 0xcb": {
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|
"ExpectedInstructionCount": 5,
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|
"Comment": [
|
|
"0x03",
|
|
"add bx, cx but modrm.rm as source"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"lsl w0, w5, #16",
|
|
"cmn w0, w7, lsl #16",
|
|
"add w26, w5, w7",
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|
"bfxil x5, x26, #0, #16"
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|
]
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|
},
|
|
"db 0x03, 0xcb": {
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|
"ExpectedInstructionCount": 3,
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|
"Comment": [
|
|
"0x03",
|
|
"add ebx, ecx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"adds w26, w5, w7",
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|
"mov x5, x26"
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|
]
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},
|
|
"db 0x48, 0x03, 0xcb": {
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|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x03",
|
|
"add rbx, rcx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"adds x26, x5, x7",
|
|
"mov x5, x26"
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|
]
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|
},
|
|
"add al, 1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x04",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"lsl w0, w4, #24",
|
|
"cmn w0, w20, lsl #24",
|
|
"add w26, w4, #0x1 (1)",
|
|
"bfxil x4, x26, #0, #8"
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|
]
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|
},
|
|
"add ax, 1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x05",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"lsl w0, w4, #16",
|
|
"cmn w0, w20, lsl #16",
|
|
"add w26, w4, #0x1 (1)",
|
|
"bfxil x4, x26, #0, #16"
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|
]
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|
},
|
|
"add eax, 1": {
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|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x05",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"adds w26, w4, #0x1 (1)",
|
|
"mov x4, x26"
|
|
]
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|
},
|
|
"add rax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x05",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"adds x26, x4, #0x1 (1)",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"add al, -1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x04",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff",
|
|
"mvn w27, w4",
|
|
"lsl w0, w4, #24",
|
|
"cmn w0, w20, lsl #24",
|
|
"add w26, w4, #0xff (255)",
|
|
"bfxil x4, x26, #0, #8"
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|
]
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|
},
|
|
"add ax, -1": {
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|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x05",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffff",
|
|
"mvn w27, w4",
|
|
"lsl w0, w4, #16",
|
|
"cmn w0, w20, lsl #16",
|
|
"add w26, w4, w20",
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|
"bfxil x4, x26, #0, #16"
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|
]
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|
},
|
|
"add eax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x05",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"mvn w27, w4",
|
|
"adds w26, w4, w20",
|
|
"mov x4, x26"
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|
]
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|
},
|
|
"add rax, -1": {
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|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x05",
|
|
"ExpectedArm64ASM": [
|
|
"mvn w27, w4",
|
|
"subs x26, x4, #0x1 (1)",
|
|
"mov x4, x26"
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|
]
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|
},
|
|
"or bl, bh": {
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|
"ExpectedInstructionCount": 4,
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|
"Comment": "",
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|
"ExpectedArm64ASM": [
|
|
"lsr w20, w7, #8",
|
|
"orr w26, w7, w20",
|
|
"bfxil x7, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
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|
]
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|
},
|
|
"or bl, cl": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x08",
|
|
"ExpectedArm64ASM": [
|
|
"orr w26, w7, w5",
|
|
"bfxil x7, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
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|
]
|
|
},
|
|
"or bx, cx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x09",
|
|
"ExpectedArm64ASM": [
|
|
"orr w26, w7, w5",
|
|
"bfxil x7, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
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|
},
|
|
"or ebx, ecx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x09",
|
|
"ExpectedArm64ASM": [
|
|
"orr w7, w7, w5",
|
|
"mov x26, x7",
|
|
"tst w7, w7"
|
|
]
|
|
},
|
|
"or rbx, rcx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x09",
|
|
"ExpectedArm64ASM": [
|
|
"orr x7, x7, x5",
|
|
"mov x26, x7",
|
|
"tst x7, x7"
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|
]
|
|
},
|
|
"db 0x0A, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x0A",
|
|
"or bl, cl but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"orr w26, w5, w7",
|
|
"bfxil x5, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"db 0x66, 0x0B, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x0B",
|
|
"or bx, cx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"orr w26, w5, w7",
|
|
"bfxil x5, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"db 0x0B, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x0B",
|
|
"or ebx, ecx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"orr w5, w5, w7",
|
|
"mov x26, x5",
|
|
"tst w5, w5"
|
|
]
|
|
},
|
|
"db 0x48, 0x0B, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x0B",
|
|
"or rbx, rcx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"orr x5, x5, x7",
|
|
"mov x26, x5",
|
|
"tst x5, x5"
|
|
]
|
|
},
|
|
"or al, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0C",
|
|
"ExpectedArm64ASM": [
|
|
"orr w26, w4, #0x1",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"or ax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0D",
|
|
"ExpectedArm64ASM": [
|
|
"orr w26, w4, #0x1",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"or eax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0D",
|
|
"ExpectedArm64ASM": [
|
|
"orr w4, w4, #0x1",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"or rax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0D",
|
|
"ExpectedArm64ASM": [
|
|
"orr x4, x4, #0x1",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"or al, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0C",
|
|
"ExpectedArm64ASM": [
|
|
"orr w26, w4, #0xff",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"or ax, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0D",
|
|
"ExpectedArm64ASM": [
|
|
"orr w26, w4, #0xffff",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"or eax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"orr w4, w4, w20",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"or rax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0D",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"orr x4, x4, x20",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"adc bl, cl": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "0x10",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"uxtb w20, w5",
|
|
"adc w21, wzr, w20",
|
|
"add w22, w7, w21",
|
|
"uxtb w26, w22",
|
|
"cmp w26, w21",
|
|
"cset x21, lo",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x22, nzcv",
|
|
"orr w21, w22, w21, lsl #29",
|
|
"eor w20, w7, w20",
|
|
"eor w22, w26, w7",
|
|
"bic w20, w22, w20",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"bfxil x7, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"adc bx, cx": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "0x11",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"uxth w20, w5",
|
|
"adc w21, wzr, w20",
|
|
"add w22, w7, w21",
|
|
"uxth w26, w22",
|
|
"cmp w26, w21",
|
|
"cset x21, lo",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x22, nzcv",
|
|
"orr w21, w22, w21, lsl #29",
|
|
"eor w20, w7, w20",
|
|
"eor w22, w26, w7",
|
|
"bic w20, w22, w20",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"bfxil x7, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"adc ebx, ecx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x11",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"adcs w26, w7, w5",
|
|
"mov x7, x26"
|
|
]
|
|
},
|
|
"adc rbx, rcx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x11",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"adcs x26, x7, x5",
|
|
"mov x7, x26"
|
|
]
|
|
},
|
|
"db 0x12, 0xcb": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0x12",
|
|
"adc bl, cl but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"uxtb w20, w7",
|
|
"adc w21, wzr, w20",
|
|
"add w22, w5, w21",
|
|
"uxtb w26, w22",
|
|
"cmp w26, w21",
|
|
"cset x21, lo",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x22, nzcv",
|
|
"orr w21, w22, w21, lsl #29",
|
|
"eor w20, w5, w20",
|
|
"eor w22, w26, w5",
|
|
"bic w20, w22, w20",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"bfxil x5, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x66, 0x13, 0xcb": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"0x13",
|
|
"adc bx, cx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"uxth w20, w7",
|
|
"adc w21, wzr, w20",
|
|
"add w22, w5, w21",
|
|
"uxth w26, w22",
|
|
"cmp w26, w21",
|
|
"cset x21, lo",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x22, nzcv",
|
|
"orr w21, w22, w21, lsl #29",
|
|
"eor w20, w5, w20",
|
|
"eor w22, w26, w5",
|
|
"bic w20, w22, w20",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"bfxil x5, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x13, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x13",
|
|
"adc ebx, ecx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"adcs w26, w5, w7",
|
|
"mov x5, x26"
|
|
]
|
|
},
|
|
"db 0x48, 0x13, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x13",
|
|
"adc rbx, rcx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"adcs x26, x5, x7",
|
|
"mov x5, x26"
|
|
]
|
|
},
|
|
"adc al, 1": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "0x14",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"mov w20, #0x1",
|
|
"adc w20, wzr, w20",
|
|
"add w21, w4, w20",
|
|
"uxtb w26, w21",
|
|
"cmp w26, w20",
|
|
"cset x20, lo",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x21, nzcv",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"eor w21, w4, #0x1",
|
|
"eor w22, w26, w4",
|
|
"bic w21, w22, w21",
|
|
"ubfx x21, x21, #7, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"adc ax, 1": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "0x15",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"mov w20, #0x1",
|
|
"adc w20, wzr, w20",
|
|
"add w21, w4, w20",
|
|
"uxth w26, w21",
|
|
"cmp w26, w20",
|
|
"cset x20, lo",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x21, nzcv",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"eor w21, w4, #0x1",
|
|
"eor w22, w26, w4",
|
|
"bic w21, w22, w21",
|
|
"ubfx x21, x21, #15, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"bfxil x4, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"adc eax, 1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x15",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"adcs w26, w4, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"adc rax, 1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x15",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"adcs x26, x4, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"adc al, -1": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "0x14",
|
|
"ExpectedArm64ASM": [
|
|
"mvn w27, w4",
|
|
"mov w20, #0xff",
|
|
"adc w20, wzr, w20",
|
|
"add w21, w4, w20",
|
|
"uxtb w26, w21",
|
|
"cmp w26, w20",
|
|
"cset x20, lo",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x21, nzcv",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"eor w21, w4, #0xff",
|
|
"eor w22, w26, w4",
|
|
"bic w21, w22, w21",
|
|
"ubfx x21, x21, #7, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"adc ax, -1": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "0x15",
|
|
"ExpectedArm64ASM": [
|
|
"mvn w27, w4",
|
|
"mov w20, #0xffff",
|
|
"adc w20, wzr, w20",
|
|
"add w21, w4, w20",
|
|
"uxth w26, w21",
|
|
"cmp w26, w20",
|
|
"cset x20, lo",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x21, nzcv",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"eor w21, w4, #0xffff",
|
|
"eor w22, w26, w4",
|
|
"bic w21, w22, w21",
|
|
"ubfx x21, x21, #15, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"bfxil x4, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"adc eax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x15",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"mvn w27, w4",
|
|
"adcs w26, w4, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"adc rax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x15",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"mvn w27, w4",
|
|
"adcs x26, x4, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sbb bl, cl": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": "0x18",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"uxtb w20, w7",
|
|
"uxtb w21, w5",
|
|
"adc w22, wzr, w21",
|
|
"sub w23, w20, w22",
|
|
"uxtb w26, w23",
|
|
"cmp w20, w22",
|
|
"cset x22, lo",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x23, nzcv",
|
|
"orr w22, w23, w22, lsl #29",
|
|
"eor w21, w20, w21",
|
|
"eor w20, w26, w20",
|
|
"and w20, w20, w21",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w22, w20, lsl #28",
|
|
"bfxil x7, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb bx, cx": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": "0x19",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"uxth w20, w7",
|
|
"uxth w21, w5",
|
|
"adc w22, wzr, w21",
|
|
"sub w23, w20, w22",
|
|
"uxth w26, w23",
|
|
"cmp w20, w22",
|
|
"cset x22, lo",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x23, nzcv",
|
|
"orr w22, w23, w22, lsl #29",
|
|
"eor w21, w20, w21",
|
|
"eor w20, w26, w20",
|
|
"and w20, w20, w21",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w22, w20, lsl #28",
|
|
"bfxil x7, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb ebx, ecx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x19",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sbcs w26, w7, w5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x7, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb rbx, rcx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x19",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sbcs x26, x7, x5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x7, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x1A, 0xcb": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": [
|
|
"0x1A",
|
|
"sbb bl, cl but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"uxtb w20, w5",
|
|
"uxtb w21, w7",
|
|
"adc w22, wzr, w21",
|
|
"sub w23, w20, w22",
|
|
"uxtb w26, w23",
|
|
"cmp w20, w22",
|
|
"cset x22, lo",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x23, nzcv",
|
|
"orr w22, w23, w22, lsl #29",
|
|
"eor w21, w20, w21",
|
|
"eor w20, w26, w20",
|
|
"and w20, w20, w21",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w22, w20, lsl #28",
|
|
"bfxil x5, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x66, 0x1B, 0xcb": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": [
|
|
"0x1B",
|
|
"sbb bx, cx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"uxth w20, w5",
|
|
"uxth w21, w7",
|
|
"adc w22, wzr, w21",
|
|
"sub w23, w20, w22",
|
|
"uxth w26, w23",
|
|
"cmp w20, w22",
|
|
"cset x22, lo",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x23, nzcv",
|
|
"orr w22, w23, w22, lsl #29",
|
|
"eor w21, w20, w21",
|
|
"eor w20, w26, w20",
|
|
"and w20, w20, w21",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w22, w20, lsl #28",
|
|
"bfxil x5, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x1B, 0xcb": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0x1B",
|
|
"sbb ebx, ecx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sbcs w26, w5, w7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x5, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x48, 0x1B, 0xcb": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"0x1B",
|
|
"sbb rbx, rcx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sbcs x26, x5, x7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x5, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb al, 1": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": "0x1C",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"uxtb w20, w4",
|
|
"mov w21, #0x1",
|
|
"adc w21, wzr, w21",
|
|
"sub w22, w20, w21",
|
|
"uxtb w26, w22",
|
|
"cmp w20, w21",
|
|
"cset x21, lo",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x22, nzcv",
|
|
"orr w21, w22, w21, lsl #29",
|
|
"eor w22, w20, #0x1",
|
|
"eor w20, w26, w20",
|
|
"and w20, w20, w22",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb ax, 1": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": "0x1D",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"uxth w20, w4",
|
|
"mov w21, #0x1",
|
|
"adc w21, wzr, w21",
|
|
"sub w22, w20, w21",
|
|
"uxth w26, w22",
|
|
"cmp w20, w21",
|
|
"cset x21, lo",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x22, nzcv",
|
|
"orr w21, w22, w21, lsl #29",
|
|
"eor w22, w20, #0x1",
|
|
"eor w20, w26, w20",
|
|
"and w20, w20, w22",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"bfxil x4, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb eax, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x1D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb rax, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x1D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb al, -1": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": "0x1C",
|
|
"ExpectedArm64ASM": [
|
|
"mvn w27, w4",
|
|
"uxtb w20, w4",
|
|
"mov w21, #0xff",
|
|
"adc w21, wzr, w21",
|
|
"sub w22, w20, w21",
|
|
"uxtb w26, w22",
|
|
"cmp w20, w21",
|
|
"cset x21, lo",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x22, nzcv",
|
|
"orr w21, w22, w21, lsl #29",
|
|
"eor w22, w20, #0xff",
|
|
"eor w20, w26, w20",
|
|
"and w20, w20, w22",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb ax, -1": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": "0x1D",
|
|
"ExpectedArm64ASM": [
|
|
"mvn w27, w4",
|
|
"uxth w20, w4",
|
|
"mov w21, #0xffff",
|
|
"adc w21, wzr, w21",
|
|
"sub w22, w20, w21",
|
|
"uxth w26, w22",
|
|
"cmp w20, w21",
|
|
"cset x21, lo",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x22, nzcv",
|
|
"orr w21, w22, w21, lsl #29",
|
|
"eor w22, w20, #0xffff",
|
|
"eor w20, w26, w20",
|
|
"and w20, w20, w22",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"bfxil x4, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb eax, -1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x1D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"mvn w27, w4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb rax, -1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x1D",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"mvn w27, w4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"and bl, cl": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x20",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w7, w5",
|
|
"cmn wzr, w26, lsl #24",
|
|
"bfxil x7, x26, #0, #8"
|
|
]
|
|
},
|
|
"and bx, cx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x21",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w7, w5",
|
|
"cmn wzr, w26, lsl #16",
|
|
"bfxil x7, x26, #0, #16"
|
|
]
|
|
},
|
|
"and ebx, ecx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x21",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w7, w5",
|
|
"mov x7, x26"
|
|
]
|
|
},
|
|
"and rbx, rcx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x21",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x7, x5",
|
|
"mov x7, x26"
|
|
]
|
|
},
|
|
"db 0x22, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x22",
|
|
"and bl, cl but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w5, w7",
|
|
"cmn wzr, w26, lsl #24",
|
|
"bfxil x5, x26, #0, #8"
|
|
]
|
|
},
|
|
"db 0x66, 0x23, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x23",
|
|
"and bx, cx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w5, w7",
|
|
"cmn wzr, w26, lsl #16",
|
|
"bfxil x5, x26, #0, #16"
|
|
]
|
|
},
|
|
"db 0x23, 0xcb": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0x23",
|
|
"and ebx, ecx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w5, w7",
|
|
"mov x5, x26"
|
|
]
|
|
},
|
|
"db 0x48, 0x23, 0xcb": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0x23",
|
|
"and rbx, rcx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x5, x7",
|
|
"mov x5, x26"
|
|
]
|
|
},
|
|
"and al, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x24",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, #0x1",
|
|
"cmn wzr, w26, lsl #24",
|
|
"bfxil x4, x26, #0, #8"
|
|
]
|
|
},
|
|
"and ax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x25",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, #0x1",
|
|
"cmn wzr, w26, lsl #16",
|
|
"bfxil x4, x26, #0, #16"
|
|
]
|
|
},
|
|
"and eax, 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x25",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w4, #0x1",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"and rax, 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x25",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x4, #0x1",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"and al, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x24",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, #0xff",
|
|
"cmn wzr, w26, lsl #24",
|
|
"bfxil x4, x26, #0, #8"
|
|
]
|
|
},
|
|
"and ax, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x25",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, #0xffff",
|
|
"cmn wzr, w26, lsl #16",
|
|
"bfxil x4, x26, #0, #16"
|
|
]
|
|
},
|
|
"and eax, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x25",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"ands w26, w4, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"and rax, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x25",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"ands x26, x4, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sub bl, cl": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x28",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"lsl w0, w7, #24",
|
|
"cmp w0, w5, lsl #24",
|
|
"sub w26, w7, w5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x7, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub bx, cx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x29",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"lsl w0, w7, #16",
|
|
"cmp w0, w5, lsl #16",
|
|
"sub w26, w7, w5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x7, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub ebx, ecx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x29",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"subs w26, w7, w5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x7, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub rbx, rcx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x29",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"subs x26, x7, x5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x7, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x2A, 0xcb": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0x2A",
|
|
"sub bl, cl but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"lsl w0, w5, #24",
|
|
"cmp w0, w7, lsl #24",
|
|
"sub w26, w5, w7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x5, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x66, 0x2B, 0xcb": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"0x2B",
|
|
"sub bx, cx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"lsl w0, w5, #16",
|
|
"cmp w0, w7, lsl #16",
|
|
"sub w26, w5, w7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x5, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x2B, 0xcb": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0x2B",
|
|
"sub ebx, ecx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"subs w26, w5, w7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x5, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x48, 0x2B, 0xcb": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0x2B",
|
|
"sub rbx, rcx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"subs x26, x5, x7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x5, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub al, 1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x2C",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub ax, 1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x2D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x4, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub eax, 1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x2D",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs w26, w4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub rax, 1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x2D",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs x26, x4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub al, -1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x2C",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff",
|
|
"mvn w27, w4",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, #0xff (255)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub ax, -1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x2D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffff",
|
|
"mvn w27, w4",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x4, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub eax, -1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x2D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"mvn w27, w4",
|
|
"subs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub rax, -1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x2D",
|
|
"ExpectedArm64ASM": [
|
|
"mvn w27, w4",
|
|
"adds x26, x4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"xor bl, cl": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x30",
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w7, w5",
|
|
"bfxil x7, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"xor bx, cx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x31",
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w7, w5",
|
|
"bfxil x7, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"xor ebx, ecx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x31",
|
|
"ExpectedArm64ASM": [
|
|
"eor w7, w7, w5",
|
|
"mov x26, x7",
|
|
"tst w7, w7"
|
|
]
|
|
},
|
|
"xor rbx, rcx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x31",
|
|
"ExpectedArm64ASM": [
|
|
"eor x7, x7, x5",
|
|
"mov x26, x7",
|
|
"tst x7, x7"
|
|
]
|
|
},
|
|
"db 0x32, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x32",
|
|
"xor bl, cl but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w5, w7",
|
|
"bfxil x5, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"db 0x66, 0x33, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x33",
|
|
"xor bx, cx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w5, w7",
|
|
"bfxil x5, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"db 0x33, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x33",
|
|
"xor ebx, ecx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w5, w5, w7",
|
|
"mov x26, x5",
|
|
"tst w5, w5"
|
|
]
|
|
},
|
|
"db 0x48, 0x33, 0xcb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x33",
|
|
"xor rbx, rcx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor x5, x5, x7",
|
|
"mov x26, x5",
|
|
"tst x5, x5"
|
|
]
|
|
},
|
|
"xor al, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x34",
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w4, #0x1",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"xor ax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x35",
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w4, #0x1",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"xor eax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x35",
|
|
"ExpectedArm64ASM": [
|
|
"eor w4, w4, #0x1",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"xor rax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x35",
|
|
"ExpectedArm64ASM": [
|
|
"eor x4, x4, #0x1",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"cmp bl, cl": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x38",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"lsl w0, w7, #24",
|
|
"cmp w0, w5, lsl #24",
|
|
"sub w26, w7, w5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"xor al, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x34",
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w4, #0xff",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"xor ax, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x35",
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w4, #0xffff",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"xor eax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x35",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"eor w4, w4, w20",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"xor rax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x35",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"eor x4, x4, x20",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"cmp bx, cx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x39",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"lsl w0, w7, #16",
|
|
"cmp w0, w5, lsl #16",
|
|
"sub w26, w7, w5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp ebx, ecx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x39",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"subs w26, w7, w5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp rbx, rcx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x39",
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w7, w5",
|
|
"subs x26, x7, x5",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x3A, 0xcb": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0x3A",
|
|
"cmp bl, cl but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"lsl w0, w5, #24",
|
|
"cmp w0, w7, lsl #24",
|
|
"sub w26, w5, w7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x66, 0x3B, 0xcb": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"0x3B",
|
|
"cmp bx, cx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"lsl w0, w5, #16",
|
|
"cmp w0, w7, lsl #16",
|
|
"sub w26, w5, w7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x3B, 0xcb": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0x3B",
|
|
"cmp ebx, ecx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"subs w26, w5, w7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"db 0x48, 0x3B, 0xcb": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0x3B",
|
|
"cmp rbx, rcx but modrm.rm as source"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor w27, w5, w7",
|
|
"subs x26, x5, x7",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp al, 1": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x3C",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp ax, 1": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x3D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp eax, 1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x3D",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs w26, w4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp rax, 1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x3D",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs x26, x4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp al, -1": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x3C",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff",
|
|
"mvn w27, w4",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, #0xff (255)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp ax, -1": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x3D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffff",
|
|
"mvn w27, w4",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp eax, -1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x3D",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"mvn w27, w4",
|
|
"subs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp rax, -1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x3D",
|
|
"ExpectedArm64ASM": [
|
|
"mvn w27, w4",
|
|
"adds x26, x4, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"push ax": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x50",
|
|
"ExpectedArm64ASM": [
|
|
"strh w4, [x8, #-2]!"
|
|
]
|
|
},
|
|
"push rax": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x50",
|
|
"ExpectedArm64ASM": [
|
|
"str x4, [x8, #-8]!"
|
|
]
|
|
},
|
|
"pop ax": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x8f",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x8]",
|
|
"add x8, x8, #0x2 (2)",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"pop rax": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8f",
|
|
"ExpectedArm64ASM": [
|
|
"ldr x4, [x8]",
|
|
"add x8, x8, #0x8 (8)"
|
|
]
|
|
},
|
|
"movsxd rax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x63",
|
|
"ExpectedArm64ASM": [
|
|
"sxtw x4, w7"
|
|
]
|
|
},
|
|
"push word 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x68",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"strh w20, [x8, #-2]!"
|
|
]
|
|
},
|
|
"push qword 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x68",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"str x20, [x8, #-8]!"
|
|
]
|
|
},
|
|
"imul ax, bx, 257": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x69",
|
|
"ExpectedArm64ASM": [
|
|
"sxth x20, w7",
|
|
"mov w21, #0x101",
|
|
"mul x20, x20, x21",
|
|
"sbfx x21, x20, #16, #16",
|
|
"bfxil x4, x20, #0, #16",
|
|
"sbfx x20, x20, #15, #1",
|
|
"cmp x21, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"imul eax, ebx, 257": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x69",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x101",
|
|
"smull x21, w7, w20",
|
|
"asr x21, x21, #32",
|
|
"mul w4, w7, w20",
|
|
"sbfx x20, x4, #31, #1",
|
|
"cmp x21, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"imul rax, rbx, 257": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x69",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x101",
|
|
"smulh x21, x7, x20",
|
|
"mul x4, x7, x20",
|
|
"asr x20, x4, #63",
|
|
"cmp x21, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"push word -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x6a",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffff",
|
|
"strh w20, [x8, #-2]!"
|
|
]
|
|
},
|
|
"push dword -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x6a",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"str x20, [x8, #-8]!"
|
|
]
|
|
},
|
|
"push qword -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x6a",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"str x20, [x8, #-8]!"
|
|
]
|
|
},
|
|
"imul ax, bx, 3": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x6b",
|
|
"ExpectedArm64ASM": [
|
|
"sxth x20, w7",
|
|
"mov w21, #0x3",
|
|
"mul x20, x20, x21",
|
|
"sbfx x21, x20, #16, #16",
|
|
"bfxil x4, x20, #0, #16",
|
|
"sbfx x20, x20, #15, #1",
|
|
"cmp x21, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"imul eax, ebx, 3": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x6b",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3",
|
|
"smull x21, w7, w20",
|
|
"asr x21, x21, #32",
|
|
"mul w4, w7, w20",
|
|
"sbfx x20, x4, #31, #1",
|
|
"cmp x21, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"imul rax, rbx, 3": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x6b",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3",
|
|
"smulh x21, x7, x20",
|
|
"mul x4, x7, x20",
|
|
"asr x20, x4, #63",
|
|
"cmp x21, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"test al, bl": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x84",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, w7",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"test ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x84",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, w7",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"test eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x84",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w4, w7"
|
|
]
|
|
},
|
|
"test rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x84",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x4, x7"
|
|
]
|
|
},
|
|
"test al, al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x84",
|
|
"ExpectedArm64ASM": [
|
|
"mov x26, x4",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"test ax, ax": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x84",
|
|
"ExpectedArm64ASM": [
|
|
"mov x26, x4",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"test eax, eax": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x84",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w4, w4"
|
|
]
|
|
},
|
|
"test rax, rax": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x84",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x4, x4"
|
|
]
|
|
},
|
|
"xchg bl, cl": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x86",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x5",
|
|
"bfxil x20, x7, #0, #8",
|
|
"mov x21, x5",
|
|
"mov x5, x20",
|
|
"bfxil x7, x21, #0, #8"
|
|
]
|
|
},
|
|
"xchg [rax], cl": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x86",
|
|
"ExpectedArm64ASM": [
|
|
"swpalb w5, w20, [x4]",
|
|
"bfxil x5, x20, #0, #8"
|
|
]
|
|
},
|
|
"xchg bx, cx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x87",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x5",
|
|
"bfxil x20, x7, #0, #16",
|
|
"mov x21, x5",
|
|
"mov x5, x20",
|
|
"bfxil x7, x21, #0, #16"
|
|
]
|
|
},
|
|
"xchg [rax], cx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x87",
|
|
"ExpectedArm64ASM": [
|
|
"swpalh w5, w20, [x4]",
|
|
"bfxil x5, x20, #0, #16"
|
|
]
|
|
},
|
|
"xchg ebx, ecx": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x87",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w7",
|
|
"mov x21, x5",
|
|
"mov x5, x20",
|
|
"mov w7, w21"
|
|
]
|
|
},
|
|
"xchg [rax], ecx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x87",
|
|
"ExpectedArm64ASM": [
|
|
"swpal w5, w5, [x4]"
|
|
]
|
|
},
|
|
"xchg rbx, rcx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x87",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x5",
|
|
"mov x5, x7",
|
|
"mov x7, x20"
|
|
]
|
|
},
|
|
"xchg [rax], rcx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x87",
|
|
"ExpectedArm64ASM": [
|
|
"swpal x5, x5, [x4]"
|
|
]
|
|
},
|
|
"mov [rax], bl": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x88",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w7",
|
|
"strb w20, [x4]"
|
|
]
|
|
},
|
|
"mov [rax], bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x89",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w7",
|
|
"strh w20, [x4]"
|
|
]
|
|
},
|
|
"mov [rax], ebx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x89",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w7",
|
|
"str w20, [x4]"
|
|
]
|
|
},
|
|
"mov [rax], rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x89",
|
|
"ExpectedArm64ASM": [
|
|
"str x7, [x4]"
|
|
]
|
|
},
|
|
"mov bl, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8a",
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x4]",
|
|
"bfxil x7, x20, #0, #8"
|
|
]
|
|
},
|
|
"mov bx, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8b",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x4]",
|
|
"bfxil x7, x20, #0, #16"
|
|
]
|
|
},
|
|
"mov ebx, [rax]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8b",
|
|
"ExpectedArm64ASM": [
|
|
"ldr w7, [x4]"
|
|
]
|
|
},
|
|
"mov rbx, [rax]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8b",
|
|
"ExpectedArm64ASM": [
|
|
"ldr x7, [x4]"
|
|
]
|
|
},
|
|
"mov ax, cs": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x28, #930]",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"mov eax, cs": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w4, [x28, #930]"
|
|
]
|
|
},
|
|
"mov rax, cs": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w4, [x28, #930]"
|
|
]
|
|
},
|
|
"mov ax, es": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x28, #928]",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"mov eax, es": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w4, [x28, #928]"
|
|
]
|
|
},
|
|
"mov rax, es": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w4, [x28, #928]"
|
|
]
|
|
},
|
|
"mov ax, ss": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x28, #932]",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"mov eax, ss": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w4, [x28, #932]"
|
|
]
|
|
},
|
|
"mov rax, ss": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w4, [x28, #932]"
|
|
]
|
|
},
|
|
"mov ax, ds": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x28, #934]",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"mov eax, ds": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w4, [x28, #934]"
|
|
]
|
|
},
|
|
"mov rax, ds": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w4, [x28, #934]"
|
|
]
|
|
},
|
|
"mov ax, gs": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"and x4, x4, #0xffffffffffff0000"
|
|
]
|
|
},
|
|
"mov eax, gs": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"mov w4, #0x0"
|
|
]
|
|
},
|
|
"mov rax, gs": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"mov w4, #0x0"
|
|
]
|
|
},
|
|
"mov ax, fs": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"and x4, x4, #0xffffffffffff0000"
|
|
]
|
|
},
|
|
"mov eax, fs": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"mov w4, #0x0"
|
|
]
|
|
},
|
|
"mov rax, fs": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8c",
|
|
"ExpectedArm64ASM": [
|
|
"mov w4, #0x0"
|
|
]
|
|
},
|
|
"lea ax, [rbx+rcx*1 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"lea eax, [rbx+rcx*1 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea rax, [rbx+rcx*1 + 0]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x4, x7, x5"
|
|
]
|
|
},
|
|
"lea ax, [rbx+rcx*2 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #1",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"lea eax, [rbx+rcx*2 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #1",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea rax, [rbx+rcx*2 + 0]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x4, x7, x5, lsl #1"
|
|
]
|
|
},
|
|
"lea ax, [rbx+rcx*4 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #2",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"lea eax, [rbx+rcx*4 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #2",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea rax, [rbx+rcx*4 + 0]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x4, x7, x5, lsl #2"
|
|
]
|
|
},
|
|
"lea ax, [rbx+rcx*8 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #3",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"lea eax, [rbx+rcx*8 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #3",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea rax, [rbx+rcx*8 + 0]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x4, x7, x5, lsl #3"
|
|
]
|
|
},
|
|
"lea ax, [ebx+ecx*1 + 0]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5",
|
|
"mov w20, w20",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"lea eax, [ebx+ecx*1 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea rax, [ebx+ecx*1 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea ax, [ebx+ecx*2 + 0]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #1",
|
|
"mov w20, w20",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"lea eax, [ebx+ecx*2 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #1",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea rax, [ebx+ecx*2 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #1",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea ax, [ebx+ecx*4 + 0]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #2",
|
|
"mov w20, w20",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"lea eax, [ebx+ecx*4 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #2",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea rax, [ebx+ecx*4 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #2",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea ax, [ebx+ecx*8 + 0]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #3",
|
|
"mov w20, w20",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"lea eax, [ebx+ecx*8 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #3",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"lea rax, [ebx+ecx*8 + 0]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x8d",
|
|
"ExpectedArm64ASM": [
|
|
"add x20, x7, x5, lsl #3",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"mov cs, ax": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Skip": "Yes",
|
|
"Comment": "0x8e"
|
|
},
|
|
"mov es, ax": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x8e",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"strh w20, [x28, #928]",
|
|
"ubfx w20, w20, #3, #13",
|
|
"add x0, x28, x20, lsl #2",
|
|
"ldr w20, [x0, #1168]",
|
|
"str w20, [x28, #944]"
|
|
]
|
|
},
|
|
"mov ss, ax": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x8e",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"strh w20, [x28, #932]",
|
|
"ubfx w20, w20, #3, #13",
|
|
"add x0, x28, x20, lsl #2",
|
|
"ldr w20, [x0, #1168]",
|
|
"str w20, [x28, #952]"
|
|
]
|
|
},
|
|
"mov ds, ax": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x8e",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"strh w20, [x28, #934]",
|
|
"ubfx w20, w20, #3, #13",
|
|
"add x0, x28, x20, lsl #2",
|
|
"ldr w20, [x0, #1168]",
|
|
"str w20, [x28, #956]"
|
|
]
|
|
},
|
|
"mov gs, ax": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Skip": "Yes",
|
|
"Comment": "0x8e"
|
|
},
|
|
"mov fs, ax": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Skip": "Yes",
|
|
"Comment": "0x8e"
|
|
},
|
|
"pop word [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x8f",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x8]",
|
|
"add x8, x8, #0x2 (2)",
|
|
"strh w20, [x4]"
|
|
]
|
|
},
|
|
"pop qword [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x8f",
|
|
"ExpectedArm64ASM": [
|
|
"ldr x20, [x8]",
|
|
"add x8, x8, #0x8 (8)",
|
|
"str x20, [x4]"
|
|
]
|
|
},
|
|
"xchg ax, bx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x90",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x7",
|
|
"bfxil x20, x4, #0, #16",
|
|
"mov x21, x7",
|
|
"mov x7, x20",
|
|
"bfxil x4, x21, #0, #16"
|
|
]
|
|
},
|
|
"xchg eax, ebx": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x90",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"mov x21, x7",
|
|
"mov x7, x20",
|
|
"mov w4, w21"
|
|
]
|
|
},
|
|
"xchg rax, rbx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x90",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x7",
|
|
"mov x7, x4",
|
|
"mov x4, x20"
|
|
]
|
|
},
|
|
"nop": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Comment": "0x90",
|
|
"ExpectedArm64ASM": []
|
|
},
|
|
"cbw": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x98",
|
|
"ExpectedArm64ASM": [
|
|
"sxtb w20, w4",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cwde": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x98",
|
|
"ExpectedArm64ASM": [
|
|
"sxth w4, w4"
|
|
]
|
|
},
|
|
"cdqe": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x98",
|
|
"ExpectedArm64ASM": [
|
|
"sxtw x4, w4"
|
|
]
|
|
},
|
|
"cwd": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x98",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"sbfx x20, x20, #15, #1",
|
|
"bfxil x6, x20, #0, #16"
|
|
]
|
|
},
|
|
"cdq": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x99",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"sbfx x20, x20, #31, #1",
|
|
"mov w6, w20"
|
|
]
|
|
},
|
|
"cqo": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x99",
|
|
"ExpectedArm64ASM": [
|
|
"asr x6, x4, #63"
|
|
]
|
|
},
|
|
"fwait": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Comment": "0x9b",
|
|
"ExpectedArm64ASM": []
|
|
},
|
|
"pushf": {
|
|
"ExpectedInstructionCount": 39,
|
|
"Comment": "0x9c",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"eor w21, w27, w26",
|
|
"ubfx w21, w21, #4, #1",
|
|
"orr x20, x20, x21, lsl #4",
|
|
"ldrb w21, [x28, #984]",
|
|
"orr x20, x20, x21, lsl #8",
|
|
"ldrb w21, [x28, #985]",
|
|
"orr x20, x20, x21, lsl #9",
|
|
"ldrsb x21, [x28, #986]",
|
|
"lsr x21, x21, #63",
|
|
"orr x20, x20, x21, lsl #10",
|
|
"cset w21, vs",
|
|
"orr x20, x20, x21, lsl #11",
|
|
"ldrb w21, [x28, #988]",
|
|
"orr x20, x20, x21, lsl #12",
|
|
"ldrb w21, [x28, #990]",
|
|
"orr x20, x20, x21, lsl #14",
|
|
"ldrb w21, [x28, #992]",
|
|
"orr x20, x20, x21, lsl #16",
|
|
"ldrb w21, [x28, #993]",
|
|
"orr x20, x20, x21, lsl #17",
|
|
"ldrb w21, [x28, #994]",
|
|
"orr x20, x20, x21, lsl #18",
|
|
"ldrb w21, [x28, #995]",
|
|
"orr x20, x20, x21, lsl #19",
|
|
"ldrb w21, [x28, #996]",
|
|
"orr x20, x20, x21, lsl #20",
|
|
"ldrb w21, [x28, #997]",
|
|
"orr x20, x20, x21, lsl #21",
|
|
"eor w21, w26, w26, lsr #4",
|
|
"eor w21, w21, w21, lsr #2",
|
|
"eor w21, w21, w21, lsr #1",
|
|
"orr x21, x21, #0xfffffffffffffffe",
|
|
"orn x20, x20, x21, ror #62",
|
|
"mrs x21, nzcv",
|
|
"and x21, x21, #0xc0000000",
|
|
"orr x20, x20, x21, lsr #24",
|
|
"orr x20, x20, #0x2",
|
|
"str x20, [x8, #-8]!"
|
|
]
|
|
},
|
|
"pushfq": {
|
|
"ExpectedInstructionCount": 39,
|
|
"Comment": "0x9c",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"eor w21, w27, w26",
|
|
"ubfx w21, w21, #4, #1",
|
|
"orr x20, x20, x21, lsl #4",
|
|
"ldrb w21, [x28, #984]",
|
|
"orr x20, x20, x21, lsl #8",
|
|
"ldrb w21, [x28, #985]",
|
|
"orr x20, x20, x21, lsl #9",
|
|
"ldrsb x21, [x28, #986]",
|
|
"lsr x21, x21, #63",
|
|
"orr x20, x20, x21, lsl #10",
|
|
"cset w21, vs",
|
|
"orr x20, x20, x21, lsl #11",
|
|
"ldrb w21, [x28, #988]",
|
|
"orr x20, x20, x21, lsl #12",
|
|
"ldrb w21, [x28, #990]",
|
|
"orr x20, x20, x21, lsl #14",
|
|
"ldrb w21, [x28, #992]",
|
|
"orr x20, x20, x21, lsl #16",
|
|
"ldrb w21, [x28, #993]",
|
|
"orr x20, x20, x21, lsl #17",
|
|
"ldrb w21, [x28, #994]",
|
|
"orr x20, x20, x21, lsl #18",
|
|
"ldrb w21, [x28, #995]",
|
|
"orr x20, x20, x21, lsl #19",
|
|
"ldrb w21, [x28, #996]",
|
|
"orr x20, x20, x21, lsl #20",
|
|
"ldrb w21, [x28, #997]",
|
|
"orr x20, x20, x21, lsl #21",
|
|
"eor w21, w26, w26, lsr #4",
|
|
"eor w21, w21, w21, lsr #2",
|
|
"eor w21, w21, w21, lsr #1",
|
|
"orr x21, x21, #0xfffffffffffffffe",
|
|
"orn x20, x20, x21, ror #62",
|
|
"mrs x21, nzcv",
|
|
"and x21, x21, #0xc0000000",
|
|
"orr x20, x20, x21, lsr #24",
|
|
"orr x20, x20, #0x2",
|
|
"str x20, [x8, #-8]!"
|
|
]
|
|
},
|
|
"popf": {
|
|
"ExpectedInstructionCount": 39,
|
|
"Comment": "0x9d",
|
|
"ExpectedArm64ASM": [
|
|
"ldr x20, [x8]",
|
|
"add x8, x8, #0x8 (8)",
|
|
"mov w21, #0x202",
|
|
"orr x27, x20, x21",
|
|
"ubfx x20, x27, #0, #1",
|
|
"lsl x20, x20, #29",
|
|
"ubfx w21, w27, #2, #1",
|
|
"mov w22, #0x1",
|
|
"eor w26, w21, #0x1",
|
|
"ubfx x21, x27, #6, #1",
|
|
"orr w20, w20, w21, lsl #30",
|
|
"ubfx x21, x27, #7, #1",
|
|
"orr w20, w20, w21, lsl #31",
|
|
"ubfx w21, w27, #8, #1",
|
|
"strb w21, [x28, #984]",
|
|
"ubfx w21, w27, #9, #1",
|
|
"strb w21, [x28, #985]",
|
|
"ubfx w21, w27, #10, #1",
|
|
"sub x21, x22, x21, lsl #1",
|
|
"strb w21, [x28, #986]",
|
|
"ubfx x21, x27, #11, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"ubfx w21, w27, #12, #1",
|
|
"strb w21, [x28, #988]",
|
|
"ubfx w21, w27, #14, #1",
|
|
"strb w21, [x28, #990]",
|
|
"ubfx w21, w27, #16, #1",
|
|
"strb w21, [x28, #992]",
|
|
"ubfx w21, w27, #17, #1",
|
|
"strb w21, [x28, #993]",
|
|
"ubfx w21, w27, #18, #1",
|
|
"strb w21, [x28, #994]",
|
|
"ubfx w21, w27, #19, #1",
|
|
"strb w21, [x28, #995]",
|
|
"ubfx w21, w27, #20, #1",
|
|
"strb w21, [x28, #996]",
|
|
"ubfx w21, w27, #21, #1",
|
|
"strb w21, [x28, #997]",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sahf": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "0x9e",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx w20, w4, #8, #8",
|
|
"mov w21, #0x28",
|
|
"bic x20, x20, x21",
|
|
"orr x27, x20, #0x2",
|
|
"ubfx x20, x27, #0, #1",
|
|
"mrs x21, nzcv",
|
|
"bfi w21, w20, #29, #1",
|
|
"ubfx w20, w27, #2, #1",
|
|
"eor w26, w20, #0x1",
|
|
"ubfx x20, x27, #6, #1",
|
|
"bfi w21, w20, #30, #1",
|
|
"ubfx x20, x27, #7, #1",
|
|
"bfi w21, w20, #31, #1",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"lahf": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "0x9f",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"eor w21, w27, w26",
|
|
"ubfx w21, w21, #4, #1",
|
|
"orr x20, x20, x21, lsl #4",
|
|
"eor w21, w26, w26, lsr #4",
|
|
"eor w21, w21, w21, lsr #2",
|
|
"eor w21, w21, w21, lsr #1",
|
|
"orr x21, x21, #0xfffffffffffffffe",
|
|
"orn x20, x20, x21, ror #62",
|
|
"mrs x21, nzcv",
|
|
"and x21, x21, #0xc0000000",
|
|
"orr x20, x20, x21, lsr #24",
|
|
"orr x20, x20, #0x2",
|
|
"bfi x4, x20, #8, #8"
|
|
]
|
|
},
|
|
"db 0x48, 0xa1; dq 0x00000000e0000008": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"mov rax, [0xe0000008]",
|
|
"0xa1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0x6264",
|
|
"movk x20, #0x3020, lsl #16",
|
|
"movk x20, #0x3678, lsl #32",
|
|
"movk x20, #0x2c37, lsl #48",
|
|
"ldr x4, [x20]"
|
|
]
|
|
},
|
|
"db 0x67, 0xa1; dd 0xe0000000": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"mov eax, [0xe0000000]",
|
|
"0xa1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x6264",
|
|
"movk w20, #0x3020, lsl #16",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"db 0x48, 0xa3; dq 0x00000000e0000008": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"mov [0xe0000008], rax",
|
|
"0xa3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0x6264",
|
|
"movk x20, #0x3020, lsl #16",
|
|
"movk x20, #0x3678, lsl #32",
|
|
"movk x20, #0x2c37, lsl #48",
|
|
"str x4, [x20]"
|
|
]
|
|
},
|
|
"db 0x67, 0xa3; dd 0xe0000000": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"mov [0xe0000000], eax",
|
|
"0xa3"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"mov w21, #0x6f6d",
|
|
"movk w21, #0x7376, lsl #16",
|
|
"str w20, [x21]"
|
|
]
|
|
},
|
|
"movsb": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xa4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x10]",
|
|
"strb w20, [x11]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"add x10, x10, x20",
|
|
"add x11, x11, x20"
|
|
]
|
|
},
|
|
"movsw": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xa5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x10]",
|
|
"strh w20, [x11]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsl x20, x20, #1",
|
|
"add x10, x10, x20",
|
|
"add x11, x11, x20"
|
|
]
|
|
},
|
|
"movsd": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xa5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x10]",
|
|
"str w20, [x11]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsl x20, x20, #2",
|
|
"add x10, x10, x20",
|
|
"add x11, x11, x20"
|
|
]
|
|
},
|
|
"movsq": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0xa5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x20, [x10]",
|
|
"str x20, [x11]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsl x20, x20, #3",
|
|
"add x10, x10, x20",
|
|
"add x11, x11, x20"
|
|
]
|
|
},
|
|
"rep movsb": {
|
|
"ExpectedInstructionCount": 83,
|
|
"Comment": "0xa4",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"mov x0, x5",
|
|
"mov x1, x11",
|
|
"mov x2, x10",
|
|
"tbnz w20, #1, #+0x94",
|
|
"cbz x0, #+0x78",
|
|
"sub x3, x1, x2",
|
|
"tbz x3, #63, #+0x8",
|
|
"neg x3, x3",
|
|
"sub x3, x3, #0x20 (32)",
|
|
"tbnz x3, #63, #+0x54",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x44",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x1c",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"sub x0, x0, #0x40 (64)",
|
|
"tbz x0, #63, #-0x14",
|
|
"add x0, x0, #0x40 (64)",
|
|
"cbz x0, #+0x34",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x20 (32)",
|
|
"cbz x0, #+0x14",
|
|
"ldrb w3, [x2], #1",
|
|
"strb w3, [x1], #1",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0xc",
|
|
"mov x0, x11",
|
|
"mov x1, x10",
|
|
"mov x2, x5",
|
|
"add x20, x0, x2",
|
|
"add x21, x1, x2",
|
|
"b #+0xa0",
|
|
"cbz x0, #+0x88",
|
|
"sub x3, x1, x2",
|
|
"tbz x3, #63, #+0x8",
|
|
"neg x3, x3",
|
|
"sub x3, x3, #0x20 (32)",
|
|
"tbnz x3, #63, #+0x64",
|
|
"sub x1, x1, #0x1f (31)",
|
|
"sub x2, x2, #0x1f (31)",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x44",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x1c",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"sub x0, x0, #0x40 (64)",
|
|
"tbz x0, #63, #-0x14",
|
|
"add x0, x0, #0x40 (64)",
|
|
"cbz x0, #+0x3c",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x20 (32)",
|
|
"cbz x0, #+0x1c",
|
|
"add x1, x1, #0x1f (31)",
|
|
"add x2, x2, #0x1f (31)",
|
|
"ldrb w3, [x2], #-1",
|
|
"strb w3, [x1], #-1",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0xc",
|
|
"mov x0, x11",
|
|
"mov x1, x10",
|
|
"mov x2, x5",
|
|
"sub x20, x0, x2",
|
|
"sub x21, x1, x2",
|
|
"mov x10, x21",
|
|
"mov x11, x20",
|
|
"mov w5, #0x0"
|
|
]
|
|
},
|
|
"rep movsw": {
|
|
"ExpectedInstructionCount": 83,
|
|
"Comment": "0xa5",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"mov x0, x5",
|
|
"mov x1, x11",
|
|
"mov x2, x10",
|
|
"tbnz w20, #1, #+0x94",
|
|
"cbz x0, #+0x78",
|
|
"sub x3, x1, x2",
|
|
"tbz x3, #63, #+0x8",
|
|
"neg x3, x3",
|
|
"sub x3, x3, #0x20 (32)",
|
|
"tbnz x3, #63, #+0x54",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x44",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x1c",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbz x0, #63, #-0x14",
|
|
"add x0, x0, #0x20 (32)",
|
|
"cbz x0, #+0x34",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x10 (16)",
|
|
"cbz x0, #+0x14",
|
|
"ldrh w3, [x2], #2",
|
|
"strh w3, [x1], #2",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0xc",
|
|
"mov x0, x11",
|
|
"mov x1, x10",
|
|
"mov x2, x5",
|
|
"add x20, x0, x2, lsl #1",
|
|
"add x21, x1, x2, lsl #1",
|
|
"b #+0xa0",
|
|
"cbz x0, #+0x88",
|
|
"sub x3, x1, x2",
|
|
"tbz x3, #63, #+0x8",
|
|
"neg x3, x3",
|
|
"sub x3, x3, #0x20 (32)",
|
|
"tbnz x3, #63, #+0x64",
|
|
"sub x1, x1, #0x1e (30)",
|
|
"sub x2, x2, #0x1e (30)",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x44",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x1c",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbz x0, #63, #-0x14",
|
|
"add x0, x0, #0x20 (32)",
|
|
"cbz x0, #+0x3c",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x10 (16)",
|
|
"cbz x0, #+0x1c",
|
|
"add x1, x1, #0x1e (30)",
|
|
"add x2, x2, #0x1e (30)",
|
|
"ldrh w3, [x2], #-2",
|
|
"strh w3, [x1], #-2",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0xc",
|
|
"mov x0, x11",
|
|
"mov x1, x10",
|
|
"mov x2, x5",
|
|
"sub x20, x0, x2, lsl #1",
|
|
"sub x21, x1, x2, lsl #1",
|
|
"mov x10, x21",
|
|
"mov x11, x20",
|
|
"mov w5, #0x0"
|
|
]
|
|
},
|
|
"rep movsd": {
|
|
"ExpectedInstructionCount": 83,
|
|
"Comment": "0xa5",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"mov x0, x5",
|
|
"mov x1, x11",
|
|
"mov x2, x10",
|
|
"tbnz w20, #1, #+0x94",
|
|
"cbz x0, #+0x78",
|
|
"sub x3, x1, x2",
|
|
"tbz x3, #63, #+0x8",
|
|
"neg x3, x3",
|
|
"sub x3, x3, #0x20 (32)",
|
|
"tbnz x3, #63, #+0x54",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x44",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x1c",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbz x0, #63, #-0x14",
|
|
"add x0, x0, #0x10 (16)",
|
|
"cbz x0, #+0x34",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x8 (8)",
|
|
"cbz x0, #+0x14",
|
|
"ldr w3, [x2], #4",
|
|
"str w3, [x1], #4",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0xc",
|
|
"mov x0, x11",
|
|
"mov x1, x10",
|
|
"mov x2, x5",
|
|
"add x20, x0, x2, lsl #2",
|
|
"add x21, x1, x2, lsl #2",
|
|
"b #+0xa0",
|
|
"cbz x0, #+0x88",
|
|
"sub x3, x1, x2",
|
|
"tbz x3, #63, #+0x8",
|
|
"neg x3, x3",
|
|
"sub x3, x3, #0x20 (32)",
|
|
"tbnz x3, #63, #+0x64",
|
|
"sub x1, x1, #0x1c (28)",
|
|
"sub x2, x2, #0x1c (28)",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x44",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x1c",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbz x0, #63, #-0x14",
|
|
"add x0, x0, #0x10 (16)",
|
|
"cbz x0, #+0x3c",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x8 (8)",
|
|
"cbz x0, #+0x1c",
|
|
"add x1, x1, #0x1c (28)",
|
|
"add x2, x2, #0x1c (28)",
|
|
"ldr w3, [x2], #-4",
|
|
"str w3, [x1], #-4",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0xc",
|
|
"mov x0, x11",
|
|
"mov x1, x10",
|
|
"mov x2, x5",
|
|
"sub x20, x0, x2, lsl #2",
|
|
"sub x21, x1, x2, lsl #2",
|
|
"mov x10, x21",
|
|
"mov x11, x20",
|
|
"mov w5, #0x0"
|
|
]
|
|
},
|
|
"rep movsq": {
|
|
"ExpectedInstructionCount": 83,
|
|
"Comment": "0xa5",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"mov x0, x5",
|
|
"mov x1, x11",
|
|
"mov x2, x10",
|
|
"tbnz w20, #1, #+0x94",
|
|
"cbz x0, #+0x78",
|
|
"sub x3, x1, x2",
|
|
"tbz x3, #63, #+0x8",
|
|
"neg x3, x3",
|
|
"sub x3, x3, #0x20 (32)",
|
|
"tbnz x3, #63, #+0x54",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x44",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x1c",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbz x0, #63, #-0x14",
|
|
"add x0, x0, #0x8 (8)",
|
|
"cbz x0, #+0x34",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"ldp q0, q1, [x2], #32",
|
|
"stp q0, q1, [x1], #32",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x4 (4)",
|
|
"cbz x0, #+0x14",
|
|
"ldr x3, [x2], #8",
|
|
"str x3, [x1], #8",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0xc",
|
|
"mov x0, x11",
|
|
"mov x1, x10",
|
|
"mov x2, x5",
|
|
"add x20, x0, x2, lsl #3",
|
|
"add x21, x1, x2, lsl #3",
|
|
"b #+0xa0",
|
|
"cbz x0, #+0x88",
|
|
"sub x3, x1, x2",
|
|
"tbz x3, #63, #+0x8",
|
|
"neg x3, x3",
|
|
"sub x3, x3, #0x20 (32)",
|
|
"tbnz x3, #63, #+0x64",
|
|
"sub x1, x1, #0x18 (24)",
|
|
"sub x2, x2, #0x18 (24)",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x44",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x1c",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbz x0, #63, #-0x14",
|
|
"add x0, x0, #0x8 (8)",
|
|
"cbz x0, #+0x3c",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"ldp q0, q1, [x2], #-32",
|
|
"stp q0, q1, [x1], #-32",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x4 (4)",
|
|
"cbz x0, #+0x1c",
|
|
"add x1, x1, #0x18 (24)",
|
|
"add x2, x2, #0x18 (24)",
|
|
"ldr x3, [x2], #-8",
|
|
"str x3, [x1], #-8",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0xc",
|
|
"mov x0, x11",
|
|
"mov x1, x10",
|
|
"mov x2, x5",
|
|
"sub x20, x0, x2, lsl #3",
|
|
"sub x21, x1, x2, lsl #3",
|
|
"mov x10, x21",
|
|
"mov x11, x20",
|
|
"mov w5, #0x0"
|
|
]
|
|
},
|
|
"cmpsb": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"0xa6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x11]",
|
|
"ldrb w21, [x10]",
|
|
"ldrsb x22, [x28, #986]",
|
|
"add x11, x11, x22",
|
|
"add x10, x10, x22",
|
|
"eor w27, w21, w20",
|
|
"lsl w0, w21, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w21, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmpsw": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"0xa7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x11]",
|
|
"ldrh w21, [x10]",
|
|
"ldrsb x22, [x28, #986]",
|
|
"lsl x22, x22, #1",
|
|
"add x11, x11, x22",
|
|
"add x10, x10, x22",
|
|
"eor w27, w21, w20",
|
|
"lsl w0, w21, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w21, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmpsd": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xa7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x11]",
|
|
"ldr w21, [x10]",
|
|
"ldrsb x22, [x28, #986]",
|
|
"lsl x22, x22, #2",
|
|
"add x11, x11, x22",
|
|
"add x10, x10, x22",
|
|
"eor w27, w21, w20",
|
|
"subs w26, w21, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmpsq": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"0xa7"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x20, [x11]",
|
|
"ldr x21, [x10]",
|
|
"ldrsb x22, [x28, #986]",
|
|
"lsl x22, x22, #3",
|
|
"add x11, x11, x22",
|
|
"add x10, x10, x22",
|
|
"eor w27, w21, w20",
|
|
"subs x26, x21, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"repz cmpsb": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": "0xa6",
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x74",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x24",
|
|
"ldrb w26, [x11]",
|
|
"ldrb w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x1 (1)",
|
|
"add x10, x10, #0x1 (1)",
|
|
"ccmp x27, x26, #nzcv, ne",
|
|
"b.eq #-0x18",
|
|
"b #+0x20",
|
|
"ldrb w26, [x11]",
|
|
"ldrb w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x1 (1)",
|
|
"sub x10, x10, #0x1 (1)",
|
|
"ccmp x27, x26, #nzcv, ne",
|
|
"b.eq #-0x18",
|
|
"eor w20, w27, w26",
|
|
"mov x21, x27",
|
|
"mov x27, x20",
|
|
"lsl w0, w21, #24",
|
|
"cmp w0, w26, lsl #24",
|
|
"sub w26, w21, w26",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"repz cmpsw": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": "0xa7",
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x74",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x24",
|
|
"ldrh w26, [x11]",
|
|
"ldrh w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x2 (2)",
|
|
"add x10, x10, #0x2 (2)",
|
|
"ccmp x27, x26, #nzcv, ne",
|
|
"b.eq #-0x18",
|
|
"b #+0x20",
|
|
"ldrh w26, [x11]",
|
|
"ldrh w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x2 (2)",
|
|
"sub x10, x10, #0x2 (2)",
|
|
"ccmp x27, x26, #nzcv, ne",
|
|
"b.eq #-0x18",
|
|
"eor w20, w27, w26",
|
|
"mov x21, x27",
|
|
"mov x27, x20",
|
|
"lsl w0, w21, #16",
|
|
"cmp w0, w26, lsl #16",
|
|
"sub w26, w21, w26",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"repz cmpsd": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": "0xa7",
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x6c",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x24",
|
|
"ldr w26, [x11]",
|
|
"ldr w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x4 (4)",
|
|
"add x10, x10, #0x4 (4)",
|
|
"ccmp x27, x26, #nzcv, ne",
|
|
"b.eq #-0x18",
|
|
"b #+0x20",
|
|
"ldr w26, [x11]",
|
|
"ldr w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x4 (4)",
|
|
"sub x10, x10, #0x4 (4)",
|
|
"ccmp x27, x26, #nzcv, ne",
|
|
"b.eq #-0x18",
|
|
"eor w20, w27, w26",
|
|
"mov x21, x27",
|
|
"mov x27, x20",
|
|
"subs w26, w21, w26",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"repz cmpsq": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": "0xa7",
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x6c",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x24",
|
|
"ldr x26, [x11]",
|
|
"ldr x27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x8 (8)",
|
|
"add x10, x10, #0x8 (8)",
|
|
"ccmp x27, x26, #nzcv, ne",
|
|
"b.eq #-0x18",
|
|
"b #+0x20",
|
|
"ldr x26, [x11]",
|
|
"ldr x27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x8 (8)",
|
|
"sub x10, x10, #0x8 (8)",
|
|
"ccmp x27, x26, #nzcv, ne",
|
|
"b.eq #-0x18",
|
|
"eor w20, w27, w26",
|
|
"mov x21, x27",
|
|
"mov x27, x20",
|
|
"subs x26, x21, x26",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"repnz cmpsb": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": "0xa6",
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x74",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x24",
|
|
"ldrb w26, [x11]",
|
|
"ldrb w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x1 (1)",
|
|
"add x10, x10, #0x1 (1)",
|
|
"ccmp x27, x26, #nZcv, ne",
|
|
"b.ne #-0x18",
|
|
"b #+0x20",
|
|
"ldrb w26, [x11]",
|
|
"ldrb w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x1 (1)",
|
|
"sub x10, x10, #0x1 (1)",
|
|
"ccmp x27, x26, #nZcv, ne",
|
|
"b.ne #-0x18",
|
|
"eor w20, w27, w26",
|
|
"mov x21, x27",
|
|
"mov x27, x20",
|
|
"lsl w0, w21, #24",
|
|
"cmp w0, w26, lsl #24",
|
|
"sub w26, w21, w26",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"repnz cmpsw": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": "0xa7",
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x74",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x24",
|
|
"ldrh w26, [x11]",
|
|
"ldrh w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x2 (2)",
|
|
"add x10, x10, #0x2 (2)",
|
|
"ccmp x27, x26, #nZcv, ne",
|
|
"b.ne #-0x18",
|
|
"b #+0x20",
|
|
"ldrh w26, [x11]",
|
|
"ldrh w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x2 (2)",
|
|
"sub x10, x10, #0x2 (2)",
|
|
"ccmp x27, x26, #nZcv, ne",
|
|
"b.ne #-0x18",
|
|
"eor w20, w27, w26",
|
|
"mov x21, x27",
|
|
"mov x27, x20",
|
|
"lsl w0, w21, #16",
|
|
"cmp w0, w26, lsl #16",
|
|
"sub w26, w21, w26",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"repnz cmpsd": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": "0xa7",
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x6c",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x24",
|
|
"ldr w26, [x11]",
|
|
"ldr w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x4 (4)",
|
|
"add x10, x10, #0x4 (4)",
|
|
"ccmp x27, x26, #nZcv, ne",
|
|
"b.ne #-0x18",
|
|
"b #+0x20",
|
|
"ldr w26, [x11]",
|
|
"ldr w27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x4 (4)",
|
|
"sub x10, x10, #0x4 (4)",
|
|
"ccmp x27, x26, #nZcv, ne",
|
|
"b.ne #-0x18",
|
|
"eor w20, w27, w26",
|
|
"mov x21, x27",
|
|
"mov x27, x20",
|
|
"subs w26, w21, w26",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"repnz cmpsq": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Comment": "0xa7",
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x6c",
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x24",
|
|
"ldr x26, [x11]",
|
|
"ldr x27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x8 (8)",
|
|
"add x10, x10, #0x8 (8)",
|
|
"ccmp x27, x26, #nZcv, ne",
|
|
"b.ne #-0x18",
|
|
"b #+0x20",
|
|
"ldr x26, [x11]",
|
|
"ldr x27, [x10]",
|
|
"subs x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x8 (8)",
|
|
"sub x10, x10, #0x8 (8)",
|
|
"ccmp x27, x26, #nZcv, ne",
|
|
"b.ne #-0x18",
|
|
"eor w20, w27, w26",
|
|
"mov x21, x27",
|
|
"mov x27, x20",
|
|
"subs x26, x21, x26",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"test al, 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xa8",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, #0x1",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"test ax, 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xa9",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, #0x1",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"test eax, 1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0xa9",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w4, #0x1"
|
|
]
|
|
},
|
|
"test rax, 1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0xa9",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x4, #0x1"
|
|
]
|
|
},
|
|
"test al, -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xa8",
|
|
"ExpectedArm64ASM": [
|
|
"mov x26, x4",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"test ax, -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xa9",
|
|
"ExpectedArm64ASM": [
|
|
"mov x26, x4",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"test eax, -1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0xa9",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w4, w4"
|
|
]
|
|
},
|
|
"test rax, -1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0xa9",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x4, x4"
|
|
]
|
|
},
|
|
"stosb": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xaa",
|
|
"ExpectedArm64ASM": [
|
|
"strb w4, [x11]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"add x11, x11, x20"
|
|
]
|
|
},
|
|
"stosw": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xab",
|
|
"ExpectedArm64ASM": [
|
|
"strh w4, [x11]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"add x11, x11, x20, lsl #1"
|
|
]
|
|
},
|
|
"stosd": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xab",
|
|
"ExpectedArm64ASM": [
|
|
"str w4, [x11]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"add x11, x11, x20, lsl #2"
|
|
]
|
|
},
|
|
"stosq": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xab",
|
|
"ExpectedArm64ASM": [
|
|
"str x4, [x11]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"add x11, x11, x20, lsl #3"
|
|
]
|
|
},
|
|
"rep stosb": {
|
|
"ExpectedInstructionCount": 55,
|
|
"Comment": "0xaa",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"ldrsb x21, [x28, #986]",
|
|
"mov x0, x5",
|
|
"mov x1, x11",
|
|
"tbnz w21, #1, #+0x64",
|
|
"cbz x0, #+0x58",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x3c",
|
|
"dup v1.16b, w20",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"stp q1, q1, [x1], #32",
|
|
"stp q1, q1, [x1], #32",
|
|
"sub x0, x0, #0x40 (64)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x40 (64)",
|
|
"cbz x0, #+0x2c",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x10",
|
|
"stp q1, q1, [x1], #32",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbz x0, #63, #-0x8",
|
|
"add x0, x0, #0x20 (32)",
|
|
"cbz x0, #+0x10",
|
|
"strb w20, [x1], #1",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0x8",
|
|
"add x11, x11, x5",
|
|
"b #+0x68",
|
|
"cbz x0, #+0x60",
|
|
"sub x1, x1, #0x1f (31)",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x3c",
|
|
"dup v1.16b, w20",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"stp q1, q1, [x1], #-32",
|
|
"stp q1, q1, [x1], #-32",
|
|
"sub x0, x0, #0x40 (64)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x40 (64)",
|
|
"cbz x0, #+0x30",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbnz x0, #63, #+0x10",
|
|
"stp q1, q1, [x1], #-32",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbz x0, #63, #-0x8",
|
|
"add x0, x0, #0x20 (32)",
|
|
"cbz x0, #+0x14",
|
|
"add x1, x1, #0x1f (31)",
|
|
"strb w20, [x1], #-1",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0x8",
|
|
"sub x11, x11, x5",
|
|
"mov w5, #0x0"
|
|
]
|
|
},
|
|
"rep stosw": {
|
|
"ExpectedInstructionCount": 55,
|
|
"Comment": "0xab",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"ldrsb x21, [x28, #986]",
|
|
"mov x0, x5",
|
|
"mov x1, x11",
|
|
"tbnz w21, #1, #+0x64",
|
|
"cbz x0, #+0x58",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x3c",
|
|
"dup v1.8h, w20",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"stp q1, q1, [x1], #32",
|
|
"stp q1, q1, [x1], #32",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x20 (32)",
|
|
"cbz x0, #+0x2c",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x10",
|
|
"stp q1, q1, [x1], #32",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbz x0, #63, #-0x8",
|
|
"add x0, x0, #0x10 (16)",
|
|
"cbz x0, #+0x10",
|
|
"strh w20, [x1], #2",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0x8",
|
|
"add x11, x11, x5, lsl #1",
|
|
"b #+0x68",
|
|
"cbz x0, #+0x60",
|
|
"sub x1, x1, #0x1e (30)",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x3c",
|
|
"dup v1.8h, w20",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"stp q1, q1, [x1], #-32",
|
|
"stp q1, q1, [x1], #-32",
|
|
"sub x0, x0, #0x20 (32)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x20 (32)",
|
|
"cbz x0, #+0x30",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbnz x0, #63, #+0x10",
|
|
"stp q1, q1, [x1], #-32",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbz x0, #63, #-0x8",
|
|
"add x0, x0, #0x10 (16)",
|
|
"cbz x0, #+0x14",
|
|
"add x1, x1, #0x1e (30)",
|
|
"strh w20, [x1], #-2",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0x8",
|
|
"sub x11, x11, x5, lsl #1",
|
|
"mov w5, #0x0"
|
|
]
|
|
},
|
|
"rep stosd": {
|
|
"ExpectedInstructionCount": 55,
|
|
"Comment": "0xab",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"ldrsb x21, [x28, #986]",
|
|
"mov x0, x5",
|
|
"mov x1, x11",
|
|
"tbnz w21, #1, #+0x64",
|
|
"cbz x0, #+0x58",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x3c",
|
|
"dup v1.4s, w20",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"stp q1, q1, [x1], #32",
|
|
"stp q1, q1, [x1], #32",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x10 (16)",
|
|
"cbz x0, #+0x2c",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x10",
|
|
"stp q1, q1, [x1], #32",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbz x0, #63, #-0x8",
|
|
"add x0, x0, #0x8 (8)",
|
|
"cbz x0, #+0x10",
|
|
"str w20, [x1], #4",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0x8",
|
|
"add x11, x11, x5, lsl #2",
|
|
"b #+0x68",
|
|
"cbz x0, #+0x60",
|
|
"sub x1, x1, #0x1c (28)",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x3c",
|
|
"dup v1.4s, w20",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"stp q1, q1, [x1], #-32",
|
|
"stp q1, q1, [x1], #-32",
|
|
"sub x0, x0, #0x10 (16)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x10 (16)",
|
|
"cbz x0, #+0x30",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbnz x0, #63, #+0x10",
|
|
"stp q1, q1, [x1], #-32",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbz x0, #63, #-0x8",
|
|
"add x0, x0, #0x8 (8)",
|
|
"cbz x0, #+0x14",
|
|
"add x1, x1, #0x1c (28)",
|
|
"str w20, [x1], #-4",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0x8",
|
|
"sub x11, x11, x5, lsl #2",
|
|
"mov w5, #0x0"
|
|
]
|
|
},
|
|
"rep stosq": {
|
|
"ExpectedInstructionCount": 54,
|
|
"Comment": [
|
|
"Unrolling the loop for faster memset can be done.",
|
|
"Taking advantage of ARM MOPs instructions can be done",
|
|
"0xab"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"mov x0, x5",
|
|
"mov x1, x11",
|
|
"tbnz w20, #1, #+0x64",
|
|
"cbz x0, #+0x58",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x3c",
|
|
"dup v1.2d, x4",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"stp q1, q1, [x1], #32",
|
|
"stp q1, q1, [x1], #32",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x8 (8)",
|
|
"cbz x0, #+0x2c",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x10",
|
|
"stp q1, q1, [x1], #32",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbz x0, #63, #-0x8",
|
|
"add x0, x0, #0x4 (4)",
|
|
"cbz x0, #+0x10",
|
|
"str x4, [x1], #8",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0x8",
|
|
"add x11, x11, x5, lsl #3",
|
|
"b #+0x68",
|
|
"cbz x0, #+0x60",
|
|
"sub x1, x1, #0x18 (24)",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x3c",
|
|
"dup v1.2d, x4",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x14",
|
|
"stp q1, q1, [x1], #-32",
|
|
"stp q1, q1, [x1], #-32",
|
|
"sub x0, x0, #0x8 (8)",
|
|
"tbz x0, #63, #-0xc",
|
|
"add x0, x0, #0x8 (8)",
|
|
"cbz x0, #+0x30",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbnz x0, #63, #+0x10",
|
|
"stp q1, q1, [x1], #-32",
|
|
"sub x0, x0, #0x4 (4)",
|
|
"tbz x0, #63, #-0x8",
|
|
"add x0, x0, #0x4 (4)",
|
|
"cbz x0, #+0x14",
|
|
"add x1, x1, #0x18 (24)",
|
|
"str x4, [x1], #-8",
|
|
"sub x0, x0, #0x1 (1)",
|
|
"cbnz x0, #-0x8",
|
|
"sub x11, x11, x5, lsl #3",
|
|
"mov w5, #0x0"
|
|
]
|
|
},
|
|
"lodsb": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0xac",
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x10]",
|
|
"bfxil x4, x20, #0, #8",
|
|
"ldrsb x20, [x28, #986]",
|
|
"add x10, x10, x20"
|
|
]
|
|
},
|
|
"lodsw": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0xad",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x10]",
|
|
"bfxil x4, x20, #0, #16",
|
|
"ldrsb x20, [x28, #986]",
|
|
"add x10, x10, x20, lsl #1"
|
|
]
|
|
},
|
|
"lodsd": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xad",
|
|
"ExpectedArm64ASM": [
|
|
"ldr w4, [x10]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"add x10, x10, x20, lsl #2"
|
|
]
|
|
},
|
|
"lodsq": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xad",
|
|
"ExpectedArm64ASM": [
|
|
"ldr x4, [x10]",
|
|
"ldrsb x20, [x28, #986]",
|
|
"add x10, x10, x20, lsl #3"
|
|
]
|
|
},
|
|
"rep lodsb": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "0xac",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x20",
|
|
"cbz x5, #+0x18",
|
|
"ldrb w20, [x10]",
|
|
"bfxil x4, x20, #0, #8",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x10, x10, #0x1 (1)",
|
|
"b #-0x14",
|
|
"b #+0x1c",
|
|
"cbz x5, #+0x18",
|
|
"ldrb w20, [x10]",
|
|
"bfxil x4, x20, #0, #8",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x10, x10, #0x1 (1)",
|
|
"b #-0x14"
|
|
]
|
|
},
|
|
"rep lodsw": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "0xad",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x20",
|
|
"cbz x5, #+0x18",
|
|
"ldrh w20, [x10]",
|
|
"bfxil x4, x20, #0, #16",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x10, x10, #0x2 (2)",
|
|
"b #-0x14",
|
|
"b #+0x1c",
|
|
"cbz x5, #+0x18",
|
|
"ldrh w20, [x10]",
|
|
"bfxil x4, x20, #0, #16",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x10, x10, #0x2 (2)",
|
|
"b #-0x14"
|
|
]
|
|
},
|
|
"rep lodsd": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": "0xad",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x1c",
|
|
"cbz x5, #+0x14",
|
|
"ldr w4, [x10]",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x10, x10, #0x4 (4)",
|
|
"b #-0x10",
|
|
"b #+0x18",
|
|
"cbz x5, #+0x14",
|
|
"ldr w4, [x10]",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x10, x10, #0x4 (4)",
|
|
"b #-0x10"
|
|
]
|
|
},
|
|
"rep lodsq": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": "0xad",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x1c",
|
|
"cbz x5, #+0x14",
|
|
"ldr x4, [x10]",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x10, x10, #0x8 (8)",
|
|
"b #-0x10",
|
|
"b #+0x18",
|
|
"cbz x5, #+0x14",
|
|
"ldr x4, [x10]",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x10, x10, #0x8 (8)",
|
|
"b #-0x10"
|
|
]
|
|
},
|
|
"scasb": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0xae",
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x11]",
|
|
"ldrsb x21, [x28, #986]",
|
|
"add x11, x11, x21",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"scasw": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x11]",
|
|
"ldrsb x21, [x28, #986]",
|
|
"add x11, x11, x21, lsl #1",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"scasd": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x11]",
|
|
"ldrsb x21, [x28, #986]",
|
|
"add x11, x11, x21, lsl #2",
|
|
"eor w27, w4, w20",
|
|
"subs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"scasq": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"ldr x20, [x11]",
|
|
"ldrsb x21, [x28, #986]",
|
|
"add x11, x11, x21, lsl #3",
|
|
"eor w27, w4, w20",
|
|
"subs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"repz scasb": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": "0xae",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x38",
|
|
"cbz x5, #+0x30",
|
|
"ldrb w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x1 (1)",
|
|
"b.eq #-0x2c",
|
|
"b #+0x34",
|
|
"cbz x5, #+0x30",
|
|
"ldrb w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x1 (1)",
|
|
"b.eq #-0x2c"
|
|
]
|
|
},
|
|
"repz scasw": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": "0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x38",
|
|
"cbz x5, #+0x30",
|
|
"ldrh w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x2 (2)",
|
|
"b.eq #-0x2c",
|
|
"b #+0x34",
|
|
"cbz x5, #+0x30",
|
|
"ldrh w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x2 (2)",
|
|
"b.eq #-0x2c"
|
|
]
|
|
},
|
|
"repz scasd": {
|
|
"ExpectedInstructionCount": 25,
|
|
"Comment": "0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x30",
|
|
"cbz x5, #+0x28",
|
|
"ldr w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"subs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x4 (4)",
|
|
"b.eq #-0x24",
|
|
"b #+0x2c",
|
|
"cbz x5, #+0x28",
|
|
"ldr w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"subs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x4 (4)",
|
|
"b.eq #-0x24"
|
|
]
|
|
},
|
|
"repz scasq": {
|
|
"ExpectedInstructionCount": 25,
|
|
"Comment": "0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x30",
|
|
"cbz x5, #+0x28",
|
|
"ldr x20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"subs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x8 (8)",
|
|
"b.eq #-0x24",
|
|
"b #+0x2c",
|
|
"cbz x5, #+0x28",
|
|
"ldr x20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"subs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x8 (8)",
|
|
"b.eq #-0x24"
|
|
]
|
|
},
|
|
"repnz scasb": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": "0xae",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x38",
|
|
"cbz x5, #+0x30",
|
|
"ldrb w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x1 (1)",
|
|
"b.ne #-0x2c",
|
|
"b #+0x34",
|
|
"cbz x5, #+0x30",
|
|
"ldrb w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x1 (1)",
|
|
"b.ne #-0x2c"
|
|
]
|
|
},
|
|
"repnz scasw": {
|
|
"ExpectedInstructionCount": 29,
|
|
"Comment": "0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x38",
|
|
"cbz x5, #+0x30",
|
|
"ldrh w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x2 (2)",
|
|
"b.ne #-0x2c",
|
|
"b #+0x34",
|
|
"cbz x5, #+0x30",
|
|
"ldrh w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x2 (2)",
|
|
"b.ne #-0x2c"
|
|
]
|
|
},
|
|
"repnz scasd": {
|
|
"ExpectedInstructionCount": 25,
|
|
"Comment": "0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x30",
|
|
"cbz x5, #+0x28",
|
|
"ldr w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"subs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x4 (4)",
|
|
"b.ne #-0x24",
|
|
"b #+0x2c",
|
|
"cbz x5, #+0x28",
|
|
"ldr w20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"subs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x4 (4)",
|
|
"b.ne #-0x24"
|
|
]
|
|
},
|
|
"repnz scasq": {
|
|
"ExpectedInstructionCount": 25,
|
|
"Comment": "0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"ldrsb x20, [x28, #986]",
|
|
"lsr x20, x20, #63",
|
|
"cbz x20, #+0x8",
|
|
"b #+0x30",
|
|
"cbz x5, #+0x28",
|
|
"ldr x20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"subs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"add x11, x11, #0x8 (8)",
|
|
"b.ne #-0x24",
|
|
"b #+0x2c",
|
|
"cbz x5, #+0x28",
|
|
"ldr x20, [x11]",
|
|
"eor w27, w4, w20",
|
|
"subs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20",
|
|
"sub x5, x5, #0x1 (1)",
|
|
"sub x11, x11, #0x8 (8)",
|
|
"b.ne #-0x24"
|
|
]
|
|
},
|
|
"mov al, 0xff": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0xb0",
|
|
"ExpectedArm64ASM": [
|
|
"orr x4, x4, #0xff"
|
|
]
|
|
},
|
|
"mov al, 0x82": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xb0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x82",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"mov ax, 0xffff": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0xb8",
|
|
"ExpectedArm64ASM": [
|
|
"orr x4, x4, #0xffff"
|
|
]
|
|
},
|
|
"mov ax, 0x4243": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xb8",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x4243",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"mov eax, 0xffffffff": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"movz+movk doesn't turn in to bitfield move",
|
|
"0xb8"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w4, #0xffffffff"
|
|
]
|
|
},
|
|
"mov eax, 0x44454647": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xb8",
|
|
"ExpectedArm64ASM": [
|
|
"mov w4, #0x4647",
|
|
"movk w4, #0x4445, lsl #16"
|
|
]
|
|
},
|
|
"mov rax, 0xffffffffffffffff": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0xb8",
|
|
"ExpectedArm64ASM": [
|
|
"mov x4, #0xffffffffffffffff"
|
|
]
|
|
},
|
|
"mov rax, 0x5152535455565758": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0xb8",
|
|
"ExpectedArm64ASM": [
|
|
"mov x4, #0x5758",
|
|
"movk x4, #0x5556, lsl #16",
|
|
"movk x4, #0x5354, lsl #32",
|
|
"movk x4, #0x5152, lsl #48"
|
|
]
|
|
},
|
|
"xlat": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xd7",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"ldrb w20, [x7, x20, sxtx]",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"cmc": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xf5",
|
|
"ExpectedArm64ASM": [
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"clc": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xf8",
|
|
"ExpectedArm64ASM": [
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xdfffffff",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"stc": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xf9",
|
|
"ExpectedArm64ASM": [
|
|
"mrs x20, nzcv",
|
|
"orr w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cli": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Skip": "Yes",
|
|
"Comment": "0xfa"
|
|
},
|
|
"sti": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Skip": "Yes",
|
|
"Comment": "0xfb"
|
|
},
|
|
"cld": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xfc",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"strb w20, [x28, #986]"
|
|
]
|
|
},
|
|
"std": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xfd",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"strb w20, [x28, #986]"
|
|
]
|
|
}
|
|
}
|
|
}
|