mirror of
https://github.com/FEX-Emu/FEX.git
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149 lines
6.3 KiB
C++
149 lines
6.3 KiB
C++
// SPDX-License-Identifier: MIT
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#include "Common/CPUInfo.h"
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#include <FEXCore/Core/Context.h>
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#include <FEXCore/Core/HostFeatures.h>
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#include <FEXCore/fextl/fmt.h>
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#include <windows.h>
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#include "CPUFeatures.h"
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namespace {
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HKEY OpenProcessorKey(uint32_t Idx) {
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HKEY Out;
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auto Path = fextl::fmt::format("Hardware\\Description\\System\\CentralProcessor\\{}", Idx);
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if (RegOpenKeyExA(HKEY_LOCAL_MACHINE, Path.c_str(), 0, KEY_READ, &Out)) {
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return nullptr;
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}
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return Out;
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}
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uint64_t ReadRegU64(HKEY Key, const char* Name) {
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uint64_t Value = 0;
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DWORD Size = sizeof(Value);
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RegGetValueA(Key, nullptr, Name, 0, nullptr, &Value, &Size);
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return Value;
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}
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} // namespace
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namespace FEX::Windows {
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class CPUFeaturesFromRegistry final : public FEX::CPUFeatures {
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public:
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explicit CPUFeaturesFromRegistry(HKEY Key) {
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ISAR0.SetReg(ReadRegU64(Key, "CP 4030"));
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PFR0.SetReg(ReadRegU64(Key, "CP 4020"));
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PFR1.SetReg(ReadRegU64(Key, "CP 4021"));
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ISAR1.SetReg(ReadRegU64(Key, "CP 4031"));
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MMFR0.SetReg(ReadRegU64(Key, "CP 4038"));
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MMFR2.SetReg(ReadRegU64(Key, "CP 403A"));
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ZFR0.SetReg(ReadRegU64(Key, "CP 4024"));
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MMFR1.SetReg(ReadRegU64(Key, "CP 4039"));
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ISAR2.SetReg(ReadRegU64(Key, "CP 4032"));
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FillFeatureFlags();
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}
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};
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FEXCore::HostFeatures CPUFeatures::FetchHostFeatures(bool IsWine) {
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HKEY Key = OpenProcessorKey(0);
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if (!Key) {
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ERROR_AND_DIE_FMT("Couldn't detect CPU features");
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}
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CPUFeaturesFromRegistry Features(Key);
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uint64_t CTR = ReadRegU64(Key, "CP 5801");
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uint64_t MIDR = ReadRegU64(Key, "CP 4000");
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auto HostFeatures = FEX::FetchHostFeatures(Features, !IsWine, CTR, MIDR);
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for (uint32_t Idx = 0; Key; Key = OpenProcessorKey(++Idx)) {
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// Truncate to 32-bits, top 32-bits are all reserved in MIDR
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HostFeatures.CPUMIDRs.push_back(static_cast<uint32_t>(ReadRegU64(Key, "CP 4000")));
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RegCloseKey(Key);
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}
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HostFeatures.SupportsCPUIndexInTPIDRRO = !IsWine;
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return HostFeatures;
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}
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CPUFeatures::CPUFeatures(FEXCore::Context::Context& CTX) {
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#ifdef _M_ARM_64EC
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// Report as a 64-bit host for ARM64EC.
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CpuInfo.ProcessorArchitecture = PROCESSOR_ARCHITECTURE_AMD64;
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#else
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// Report as a 32-bit host for WoW64.
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CpuInfo.ProcessorArchitecture = PROCESSOR_ARCHITECTURE_INTEL;
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#endif
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// Baseline FEX feature-set
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CpuInfo.ProcessorFeatureBits = CPU_FEATURE_VME | CPU_FEATURE_TSC | CPU_FEATURE_CMOV | CPU_FEATURE_PGE | CPU_FEATURE_PSE | CPU_FEATURE_MTRR |
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CPU_FEATURE_CX8 | CPU_FEATURE_MMX | CPU_FEATURE_X86 | CPU_FEATURE_PAT | CPU_FEATURE_FXSR | CPU_FEATURE_SEP |
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CPU_FEATURE_SSE | CPU_FEATURE_3DNOW | CPU_FEATURE_SSE2 | CPU_FEATURE_SSE3 | CPU_FEATURE_CX128 |
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CPU_FEATURE_NX | CPU_FEATURE_SSSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_PAE | CPU_FEATURE_DAZ;
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// Features that require specific host CPU support
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const auto CPUIDResult01 = CTX.RunCPUIDFunction(0x01, 0);
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if (CPUIDResult01.ecx & (1 << 20)) {
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CpuInfo.ProcessorFeatureBits |= CPU_FEATURE_SSE42;
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}
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if (CPUIDResult01.ecx & (1 << 27)) {
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CpuInfo.ProcessorFeatureBits |= CPU_FEATURE_XSAVE;
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}
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if (CPUIDResult01.ecx & (1 << 28)) {
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CpuInfo.ProcessorFeatureBits |= CPU_FEATURE_AVX;
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}
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const auto CPUIDResult07 = CTX.RunCPUIDFunction(0x07, 0);
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if (CPUIDResult07.ebx & (1 << 5)) {
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CpuInfo.ProcessorFeatureBits |= CPU_FEATURE_AVX2;
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}
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const auto FamilyIdentifier = CPUIDResult01.eax;
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CpuInfo.ProcessorLevel = ((FamilyIdentifier >> 8) & 0xf) + ((FamilyIdentifier >> 20) & 0xff); // Family
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CpuInfo.ProcessorRevision = (FamilyIdentifier & 0xf0000) >> 4; // Extended Model
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CpuInfo.ProcessorRevision |= (FamilyIdentifier & 0xf0) << 4; // Model
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CpuInfo.ProcessorRevision |= FamilyIdentifier & 0xf; // Stepping
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}
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bool CPUFeatures::IsFeaturePresent(uint32_t Feature) {
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switch (Feature) {
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case PF_FLOATING_POINT_PRECISION_ERRATA: return FALSE;
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case PF_FLOATING_POINT_EMULATED: return FALSE;
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case PF_COMPARE_EXCHANGE_DOUBLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_CX8);
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case PF_MMX_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_MMX);
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case PF_XMMI_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_SSE);
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case PF_3DNOW_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_3DNOW);
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case PF_RDTSC_INSTRUCTION_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_TSC);
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case PF_PAE_ENABLED: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_PAE);
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case PF_XMMI64_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_SSE2);
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case PF_SSE3_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_SSE3);
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case PF_SSSE3_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_SSSE3);
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case PF_XSAVE_ENABLED: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_XSAVE);
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case PF_COMPARE_EXCHANGE128: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_CX128);
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case PF_SSE_DAZ_MODE_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_DAZ);
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case PF_NX_ENABLED: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_NX);
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case PF_SECOND_LEVEL_ADDRESS_TRANSLATION: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_2NDLEV);
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case PF_VIRT_FIRMWARE_ENABLED: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_VIRT);
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case PF_RDWRFSGSBASE_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_RDFS);
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case PF_FASTFAIL_AVAILABLE: return TRUE;
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case PF_SSE4_1_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_SSE41);
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case PF_SSE4_2_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_SSE42);
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case PF_AVX_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_AVX);
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case PF_AVX2_INSTRUCTIONS_AVAILABLE: return !!(CpuInfo.ProcessorFeatureBits & CPU_FEATURE_AVX2);
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default: return false;
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}
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}
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void CPUFeatures::UpdateInformation(SYSTEM_CPU_INFORMATION* Info) {
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Info->ProcessorArchitecture = CpuInfo.ProcessorArchitecture;
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Info->ProcessorLevel = CpuInfo.ProcessorLevel;
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Info->ProcessorRevision = CpuInfo.ProcessorRevision;
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Info->ProcessorFeatureBits = CpuInfo.ProcessorFeatureBits;
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}
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} // namespace FEX::Windows
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