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FEX-Emu--FEX/FEXCore/Source/Interface/Core/OpcodeDispatcher
Ryan Houdek a29076244f OpcodeDispatcher: Optimizes mpsadbw
Two optimizations here:
1) The final VInsElement was generating three instructions
   - This itself could have been change to vzip, which would have
     removed two instructions.
2) Optimize how the pairwise elements are calculated to shave one
   instruction off the calculation.
   - addp odd elements and even elemnts first
   - Then transpose those elements
   - Then use one final addp to generate the result in the correct
     order.

The ext+uabdl+addp pairs of operations could be reordered to shave off
one temporary register usage if we really care later.
2023-08-21 16:56:41 -07:00
..
2023-08-21 16:56:41 -07:00
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2023-08-17 16:32:16 -04:00