mirror of
https://github.com/FEX-Emu/FEX.git
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LC
a4d5fbae63
We've accumulated a bunch of forward declarations that are no longer necessary. We also don't need to pass the signal delegator as a reference, since we're not modifying the pointer itself, it's just passed in to register a signal handler.
319 lines
9.4 KiB
C++
319 lines
9.4 KiB
C++
// SPDX-License-Identifier: MIT
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#include "HostRunner.h"
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#include "ArchHelpers/UContext.h"
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#include "LinuxSyscalls/SignalDelegator.h"
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/Core/Context.h>
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#include <FEXCore/Core/CoreState.h>
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#include <FEXCore/Core/X86Enums.h>
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#include <FEXCore/Debug/InternalThreadState.h>
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#include <FEXCore/fextl/list.h>
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#include <FEXCore/fextl/unordered_map.h>
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#include <FEXCore/fextl/unordered_set.h>
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#include <FEXCore/Utils/LogManager.h>
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#ifdef ARCHITECTURE_x86_64
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#include "Common/X86Features.h"
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#include <asm/ldt.h>
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#include <sys/syscall.h>
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#endif
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#include <csignal>
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#include <cstddef>
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#include <cstdint>
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#include <cstring>
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#include <ucontext.h>
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#ifdef ARCHITECTURE_x86_64
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static inline int modify_ldt(int func, void* ldt) {
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return ::syscall(SYS_modify_ldt, func, ldt, sizeof(struct user_desc));
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}
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__attribute__((naked)) void Dispatcher(uintptr_t BranchTarget, void* ReturningStackLocation, int CodeSegment, int SupportsFSGSBase) {
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// BranchTarget: rdi
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// ReturningStackLocation: rsi
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// CodeSegment: rdx
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// SupportsFSGSBase: rcx
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__asm volatile(R"(
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.intel_syntax noprefix;
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// x86-64 ABI has the stack aligned when /call/ happens
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// Which means the destination has a misaligned stack at that point
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push rbx;
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push rbp;
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push r12;
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push r13;
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push r14;
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push r15;
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test ecx, ecx;
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je 1f;
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rdfsbase rbx;
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push rbx;
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rdgsbase rbx;
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push rbx;
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1:
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push rcx;
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// Save this stack pointer so we can cleanly shutdown the emulation with a long jump
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// regardless of where we were in the stack
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mov [rsi], rsp;
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// Clear all state going in to the branch target.
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// Only remaining state, rdi, rdx, rsp
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mov rax, 0;
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mov rbx, 0;
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mov rcx, 0;
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mov rbp, 0;
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mov rsi, 0;
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mov r8, 0;
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mov r9, 0;
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mov r10, 0;
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mov r11, 0;
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mov r12, 0;
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mov r13, 0;
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mov r14, 0;
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mov r15, 0;
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finit;
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cmp rdx, 0;
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jnz .32_bit;
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.64_bit:
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// Set flags to x86 reset state (0x202: IF=1, reserved bit 1=1).
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push 0x202;
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popfq;
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mov rdx, 0;
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mov rsp, 0;
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// Tail-call
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jmp rdi;
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.32_bit:
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// Far call needs to go through a gate
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// This is setup just like the following packing
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// {
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// uint32_t RIP;
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// uint16_t CodeSegment;
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// }
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sub rsp, 16
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mov [rsp], edi;
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mov [rsp+4], dx
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// Set flags to x86 reset state (0x202: IF=1, reserved bit 1=1).
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push 0x202;
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popfq;
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mov rdx, 0;
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GetCodeSegmentEntryLocation:
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hlt;
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jmp fword ptr [rsp];
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ThreadStopHandlerAddress:
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pop rcx
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test ecx, ecx;
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je 1f;
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pop rbx;
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wrgsbase rbx;
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pop rbx;
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wrfsbase rbx;
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1:
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pop r15;
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pop r14;
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pop r13;
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pop r12;
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pop rbp;
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pop rbx;
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ret;
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.att_syntax prefix;
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)" ::
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: "memory", "cc");
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}
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extern "C" void* GetCodeSegmentEntryLocation;
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uintptr_t GetCodeSegmentEntryLocationPtr = (uintptr_t)&GetCodeSegmentEntryLocation;
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extern "C" void* ThreadStopHandlerAddress;
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uintptr_t ThreadStopHandlerAddressPtr = (uintptr_t)&ThreadStopHandlerAddress;
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class x86HostRunner final {
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public:
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x86HostRunner() {
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Setup32BitCodeSegment();
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}
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bool HandleSIGSEGV(FEXCore::Core::CPUState* OutState, int Signal, void* info, void* ucontext) {
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ucontext_t* _context = (ucontext_t*)ucontext;
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mcontext_t* _mcontext = &_context->uc_mcontext;
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// Check our current instruction that we just executed to ensure it was an HLT
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uint8_t* Inst {};
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Inst = reinterpret_cast<uint8_t*>(_mcontext->gregs[REG_RIP]);
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if (!Is64BitMode()) {
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if (_mcontext->gregs[REG_RIP] == ::GetCodeSegmentEntryLocationPtr) {
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// Backup the CSGSFS register
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GlobalCodeSegmentEntry = _mcontext->gregs[REG_CSGSFS];
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// Skip past this hlt and keep running
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_mcontext->gregs[REG_RIP] += 1;
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return true;
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}
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}
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constexpr uint8_t HLT = 0xF4;
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if (Inst[0] != HLT) {
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return false;
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}
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// Store our host state in to the guest for testing against
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OutState->gregs[FEXCore::X86State::REG_RAX] = _mcontext->gregs[REG_RAX];
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OutState->gregs[FEXCore::X86State::REG_RBX] = _mcontext->gregs[REG_RBX];
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OutState->gregs[FEXCore::X86State::REG_RCX] = _mcontext->gregs[REG_RCX];
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OutState->gregs[FEXCore::X86State::REG_RDX] = _mcontext->gregs[REG_RDX];
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OutState->gregs[FEXCore::X86State::REG_RBP] = _mcontext->gregs[REG_RBP];
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OutState->gregs[FEXCore::X86State::REG_RSI] = _mcontext->gregs[REG_RSI];
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OutState->gregs[FEXCore::X86State::REG_RDI] = _mcontext->gregs[REG_RDI];
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OutState->gregs[FEXCore::X86State::REG_RSP] = _mcontext->gregs[REG_RSP];
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OutState->gregs[FEXCore::X86State::REG_R8] = _mcontext->gregs[REG_R8];
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OutState->gregs[FEXCore::X86State::REG_R9] = _mcontext->gregs[REG_R9];
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OutState->gregs[FEXCore::X86State::REG_R10] = _mcontext->gregs[REG_R10];
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OutState->gregs[FEXCore::X86State::REG_R11] = _mcontext->gregs[REG_R11];
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OutState->gregs[FEXCore::X86State::REG_R12] = _mcontext->gregs[REG_R12];
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OutState->gregs[FEXCore::X86State::REG_R13] = _mcontext->gregs[REG_R13];
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OutState->gregs[FEXCore::X86State::REG_R14] = _mcontext->gregs[REG_R14];
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OutState->gregs[FEXCore::X86State::REG_R15] = _mcontext->gregs[REG_R15];
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OutState->rip = _mcontext->gregs[REG_RIP];
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for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
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memcpy(&OutState->xmm.avx.data[i], &_mcontext->fpregs->_xmm[i], sizeof(_mcontext->fpregs->_xmm[0]));
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}
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const auto* xstate = reinterpret_cast<FEXCore::x86_64::xstate*>(_mcontext->fpregs);
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const auto* reserved = &xstate->fpstate.sw_reserved;
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if (reserved->HasExtendedContext() && reserved->HasYMMH()) {
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for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; i++) {
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memcpy(&OutState->xmm.avx.data[i][2], &xstate->ymmh.ymmh_space[i], sizeof(xstate->ymmh.ymmh_space[0]));
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}
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}
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const uint16_t CurrentOffset = (_mcontext->fpregs->swd >> 11) & 7;
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for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_MMS; ++i) {
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memcpy(&OutState->mm[(i + CurrentOffset) % 8], &_mcontext->fpregs->_st[i], sizeof(_mcontext->fpregs->_st[0]));
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}
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// Our thread is stopping
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// We don't care about anything at this point
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// Set the stack to our starting location when we entered the JIT and get out safely
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_mcontext->gregs[REG_RSP] = ReturningStackLocation;
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// Set the new PC
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_mcontext->gregs[REG_RIP] = ::ThreadStopHandlerAddressPtr;
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if (!Is64BitMode()) {
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// Unset code segment so we can jump back in to 64-bit mode
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_mcontext->gregs[REG_CSGSFS] = GlobalCodeSegmentEntry;
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}
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return true;
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}
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void Dispatch(uint64_t InitialRip) {
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FEX::X86::Features Feature {};
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Dispatcher(InitialRip, &ReturningStackLocation, CodeSegmentEntry, Feature.Feat_fsgsbase);
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}
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private:
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FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
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uint64_t GlobalCodeSegmentEntry {};
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int CodeSegmentEntry {};
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uint64_t ReturningStackLocation;
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uint32_t MakeSelector(int Segment, bool LDT) const {
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// Selector Index, Table Indicator (1 = LDT, 0 = GDT), CPL (3 = userland)
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return (Segment << 3) | ((uint32_t)LDT << 2) | 3;
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};
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void Setup32BitCodeSegment() {
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if (Is64BitMode()) {
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return;
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}
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struct user_desc ldt {};
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ldt.entry_number = 1;
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// This is where HarnessCodeLoader loads code to
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ldt.base_addr = 0;
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ldt.limit = ~0U; // No limit
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ldt.seg_32bit = 1; // 32-bit
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ldt.contents = MODIFY_LDT_CONTENTS_CODE;
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ldt.read_exec_only = 0;
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ldt.limit_in_pages = 1;
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ldt.seg_not_present = 0;
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ldt.useable = 1;
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ldt.lm = 0; // Not-64-bit
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int Res = modify_ldt(0x11, &ldt);
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if (Res == -1) {
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LogMan::Msg::EFmt("Couldn't load 32-bit LDT");
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return;
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}
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CodeSegmentEntry = MakeSelector(ldt.entry_number, 1);
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// Make the data segment follow directly after the code segment
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// Overlapping region makes it read/write
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ldt.entry_number = 2;
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// This is where HarnessCodeLoader loads code to
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ldt.base_addr = 0;
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ldt.limit = ~0U; // No limit
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ldt.seg_32bit = 1; // 32-bit
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ldt.contents = MODIFY_LDT_CONTENTS_DATA;
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ldt.read_exec_only = 0;
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ldt.limit_in_pages = 1;
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ldt.seg_not_present = 0;
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ldt.useable = 1;
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ldt.lm = 0; // Not-64-bit
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Res = modify_ldt(0x11, &ldt);
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if (Res == -1) {
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LogMan::Msg::EFmt("Couldn't load 32-bit LDT");
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return;
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}
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// Stack entry overlapping data
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ldt.entry_number = 3;
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// This is where HarnessCodeLoader loads code to
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ldt.base_addr = 0;
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ldt.limit = ~0U; // No limit
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ldt.seg_32bit = 1; // 32-bit
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ldt.contents = MODIFY_LDT_CONTENTS_STACK;
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ldt.read_exec_only = 0;
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ldt.limit_in_pages = 1;
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ldt.seg_not_present = 0;
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ldt.useable = 1;
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ldt.lm = 0; // Not-64-bit
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Res = modify_ldt(0x11, &ldt);
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if (Res == -1) {
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LogMan::Msg::EFmt("Couldn't load 32-bit LDT");
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return;
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}
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}
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};
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void RunAsHost(FEX::HLE::SignalDelegator* SignalDelegation, uintptr_t InitialRip, FEXCore::Core::CPUState* OutputState) {
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x86HostRunner runner;
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SignalDelegation->RegisterHostSignalHandler(
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SIGSEGV,
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[&runner, OutputState](FEXCore::Core::InternalThreadState* Thread, int Signal, void* info, void* ucontext) -> bool {
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return runner.HandleSIGSEGV(OutputState, Signal, info, ucontext);
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},
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true);
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runner.Dispatch(InitialRip);
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}
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#else
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void RunAsHost(FEX::HLE::SignalDelegator* SignalDelegation, uintptr_t InitialRip, FEXCore::Core::CPUState* OutputState) {
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LOGMAN_MSG_A_FMT("RunAsHost doesn't exist for this host");
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}
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#endif
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