mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 11:00:19 +02:00
Ryan Houdek
9e5d7aa5fe
This has the Frontend and OpcodeDispatcher select their operating mode depending on the incoming code segment long-mode flag. Adds some asserts since currently it is unexpected if the configuration changes at runtime. This is fairly straightforward for an initial setup but isn't fully fleshed out. Right now FEX's x86 tables aren't setup in a way to support choosing a different instruction decoding depending on runtime operating mode change, so that would break in interesting ways. Primarily this just gets FEX setup to start piping the operating mode through from the frontend to the backend. This is a long term task, so it is going to take a long time to iron out all the issues.
122 lines
4.0 KiB
C++
122 lines
4.0 KiB
C++
// SPDX-License-Identifier: MIT
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#pragma once
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#include "Interface/Core/X86Tables/X86Tables.h"
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#include <FEXCore/HLE/SyscallHandler.h>
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#include <FEXCore/Utils/Telemetry.h>
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#include <FEXCore/fextl/set.h>
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#include <FEXCore/fextl/vector.h>
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#include <array>
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#include <cstdint>
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#include <stddef.h>
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namespace FEXCore::Context {
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class ContextImpl;
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}
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namespace FEXCore::Frontend {
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class Decoder final {
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public:
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// New Frontend decoding
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struct DecodedBlocks final {
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uint64_t Entry{};
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uint64_t NumInstructions{};
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FEXCore::X86Tables::DecodedInst *DecodedInstructions;
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bool HasInvalidInstruction{};
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};
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struct DecodedBlockInformation final {
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uint64_t TotalInstructionCount;
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bool Is64BitMode{};
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fextl::vector<DecodedBlocks> Blocks;
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};
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Decoder(FEXCore::Context::ContextImpl *ctx);
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~Decoder();
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void DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState *Thread, uint8_t const* InstStream, uint64_t PC, uint64_t MaxInst, std::function<void(uint64_t BlockEntry, uint64_t Start, uint64_t Length)> AddContainedCodePage);
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DecodedBlockInformation const *GetDecodedBlockInfo() const {
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return &BlockInfo;
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}
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uint64_t DecodedMinAddress {};
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uint64_t DecodedMaxAddress {~0ULL};
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void SetSectionMaxAddress(uint64_t v) { SectionMaxAddress = v; }
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void SetExternalBranches(fextl::set<uint64_t> *v) { ExternalBranches = v; }
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void DelayedDisownBuffer() {
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PoolObject.DelayedDisownBuffer();
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}
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private:
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// To pass any information from instruction prefixes
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// down into the actual instruction handling machinery.
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struct DecodedHeader {
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uint8_t vvvv; // Encoded operand in a VEX prefix.
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bool w; // VEX.W bit.
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bool L; // VEX.L bit (if set then 256 bit operation, if unset then scalar or 128-bit operation)
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};
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FEXCore::Context::ContextImpl *CTX;
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const FEXCore::HLE::SyscallOSABI OSABI{};
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bool DecodeInstruction(uint64_t PC);
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void BranchTargetInMultiblockRange();
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bool BranchTargetCanContinue(bool FinalInstruction) const;
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uint8_t ReadByte();
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uint8_t PeekByte(uint8_t Offset) const;
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uint64_t ReadData(uint8_t Size);
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void SkipBytes(uint8_t Size) { InstructionSize += Size; }
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bool NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, DecodedHeader Options = {});
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bool NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op);
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static constexpr size_t DefaultDecodedBufferSize = 0x10000;
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FEXCore::X86Tables::DecodedInst *DecodedBuffer{};
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Utils::FixedSizePooledAllocation<FEXCore::X86Tables::DecodedInst*, 5000, 500> PoolObject;
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size_t DecodedSize {};
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uint8_t const *InstStream;
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uint8_t GetGPRSize() const { return BlockInfo.Is64BitMode ? 8 : 4; }
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static constexpr size_t MAX_INST_SIZE = 15;
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uint8_t InstructionSize;
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std::array<uint8_t, MAX_INST_SIZE> Instruction;
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FEXCore::X86Tables::DecodedInst *DecodeInst;
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// This is for multiblock data tracking
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bool SymbolAvailable {false};
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uint64_t EntryPoint {};
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uint64_t MaxCondBranchForward {};
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uint64_t MaxCondBranchBackwards {~0ULL};
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uint64_t SymbolMaxAddress {};
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uint64_t SymbolMinAddress {~0ULL};
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uint64_t SectionMaxAddress {~0ULL};
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DecodedBlockInformation BlockInfo;
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fextl::set<uint64_t> BlocksToDecode;
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fextl::set<uint64_t> HasBlocks;
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fextl::set<uint64_t> *ExternalBranches {nullptr};
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// ModRM rm decoding
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using DecodeModRMPtr = void (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
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void DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
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void DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
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static constexpr std::array<DecodeModRMPtr, 2> DecodeModRMs_Disp{
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&FEXCore::Frontend::Decoder::DecodeModRM_64,
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&FEXCore::Frontend::Decoder::DecodeModRM_16,
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};
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const uint8_t *AdjustAddrForSpecialRegion(uint8_t const* _InstStream, uint64_t EntryPoint, uint64_t RIP);
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FEXCORE_TELEMETRY_INIT(VEXOpTelem, TYPE_USES_VEX_OPS);
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FEXCORE_TELEMETRY_INIT(EVEXOpTelem, TYPE_USES_EVEX_OPS);
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};
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}
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