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Ryan Houdek
f44cd9c545
L1 cache residency can get quite large. Solution, start out small and scale quickly on L1 cache misses but L2/L3 cache hits. Some stats on L1 cache residency change: - Teardown: 40MB -> 16MB (40%) - Ender Lilies: 79MB -> 32MB (40.5%) - Death Stranding: 186MB -> 93MB (50%) - Steam: 75MB -> 7MB (9.3%) The cost of this option is effectively free in our JIT. It changes a single LDR to be a single LDP, which on Cortex CPUs cost the same. We do this by moving the L1 pointer mask in to the CPUState object, making it dynamic so it lives next to the L1 pointer. We then use that directly rather than having the hardcoded value. The lookup cache does a little bit of additional tracking and heuristics to determine when the current L1 cache should increase or decrease in size. From 128KB to 16MB per thread, allocating the full VA range as previously. Once the heuristic determines that L1 should be increased, it simply changes the max and the L1 pointer size to compensate, the kernel will fault in whichever pages are necessary. Decreasing the size is a little bit more complex, as we want to madvise the resulting L1 range to ensure we don't have that memory as resident anymore. Same heuristic but going in the opposite direction otherwise. Tends to be the case that L1 cache increases a bit on loading screens then backs down once in-game. These heuristic values are exposed for increasing and decreasing because while I think I've picked reasonable values, we will likely need some more fine tuning over time. Kind of expert user toggles at that point. Based on #4940 as a base which needs to be merged first. Full tracked stats from steam as an example of where we are: ``` Total (1000 millisecond sample period): JIT Time: 0.486630 ms/second (0.00 percent) Signal Time: 0.065880 ms/second (0.00 percent) SIGBUS Cnt: 38 (38.160780 per second) SMC Cnt: 0 Softfloat Cnt: 0 FEX JIT Load: 0.004585 (cycles: 552510) Total FEX Anon memory resident: 368 mB JIT resident: 95 mB OpDispatcher resident: 38 mB Frontend resident: 8 mB CPUBackend resident: 624 kB Lookup cache resident: 0 (null) Lookup L1 cache resident: 7 mB ThreadStates resident: 460 kB Unaccounted resident: 217 mB ```
107 lines
4.0 KiB
C++
107 lines
4.0 KiB
C++
// SPDX-License-Identifier: MIT
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/*
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$info$
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tags: glue|block-database
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desc: Stores information about blocks, and provides C++ implementations to lookup the blocks
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$end_info$
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*/
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#include <FEXCore/Utils/Allocator.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/HLE/SyscallHandler.h>
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#include "Interface/Context/Context.h"
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#include "Interface/Core/LookupCache.h"
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namespace FEXCore {
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GuestToHostMap::GuestToHostMap()
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: BlockLinks_mbr {"FEXMem_BlockLinks"} {
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BlockLinks_pma = fextl::make_unique<std::pmr::polymorphic_allocator<std::byte>>(&BlockLinks_mbr);
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// Setup our PMR map.
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BlockLinks = BlockLinks_pma->new_object<BlockLinksMapType>();
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}
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LookupCache::LookupCache(FEXCore::Context::ContextImpl* CTX)
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: ctx {CTX} {
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TotalCacheSize = ctx->Config.VirtualMemSize / FEXCore::Utils::FEX_PAGE_SIZE * 8 + CODE_SIZE + MAX_L1_SIZE;
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// Block cache ends up looking like this
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// PageMemoryMap[VirtualMemoryRegion >> 12]
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// |
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// v
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// PageMemory[Memory & (VIRTUAL_PAGE_SIZE - 1)]
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// |
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// v
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// Pointer to Code
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//
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// Allocate a region of memory that we can use to back our block pointers
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// We need one pointer per page of virtual memory
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// At 64GB of virtual memory this will allocate 128MB of virtual memory space
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PagePointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::VirtualAlloc(TotalCacheSize, false, false));
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FEXCore::Allocator::VirtualName("FEXMem_Lookup", reinterpret_cast<void*>(PagePointer),
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ctx->Config.VirtualMemSize / FEXCore::Utils::FEX_PAGE_SIZE * 8 + CODE_SIZE);
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CTX->SyscallHandler->MarkOvercommitRange(PagePointer, TotalCacheSize);
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// Allocate our memory backing our pages
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// We need 32KB per guest page (One pointer per byte)
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// XXX: We can drop down to 16KB if we store 4byte offsets from the code base
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// We currently limit to 128MB of real memory for caching for the total cache size.
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// Can end up being inefficient if we compile a small number of blocks per page
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PageMemory = PagePointer + ctx->Config.VirtualMemSize / FEXCore::Utils::FEX_PAGE_SIZE * 8;
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LOGMAN_THROW_A_FMT(PageMemory != -1ULL, "Failed to allocate page memory");
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// L1 Cache
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L1Pointer = PageMemory + CODE_SIZE;
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FEXCore::Allocator::VirtualName("FEXMem_Lookup_L1", reinterpret_cast<void*>(L1Pointer), MAX_L1_SIZE);
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LOGMAN_THROW_A_FMT(L1Pointer != -1ULL, "Failed to allocate L1Pointer");
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VirtualMemSize = ctx->Config.VirtualMemSize;
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if (DynamicL1Cache()) {
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// Start at minimum size when dynamic.
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L1PointerMask = MIN_L1_ENTRIES - 1;
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} else {
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// Start at maximum instead.
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L1PointerMask = MAX_L1_ENTRIES - 1;
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}
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}
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LookupCache::~LookupCache() {
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FEXCore::Allocator::VirtualFree(reinterpret_cast<void*>(PagePointer), TotalCacheSize);
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ctx->SyscallHandler->UnmarkOvercommitRange(PagePointer, TotalCacheSize);
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// No need to free BlockLinks map.
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// These will get freed when their memory allocators are deallocated.
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}
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void LookupCache::ClearL2Cache(const FEXCore::LookupCacheWriteLockToken& lk) {
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// Clear out the page memory
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// PagePointer and PageMemory are sequential with each other. Clear both at once.
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FEXCore::Allocator::VirtualDontNeed(reinterpret_cast<void*>(PagePointer),
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ctx->Config.VirtualMemSize / FEXCore::Utils::FEX_PAGE_SIZE * 8 + CODE_SIZE, false);
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AllocateOffset = 0;
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}
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void LookupCache::ClearThreadLocalCaches(const LookupCacheWriteLockToken&) {
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// Clear L1 and L2 by clearing the full cache.
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FEXCore::Allocator::VirtualDontNeed(reinterpret_cast<void*>(PagePointer), TotalCacheSize, false);
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}
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void LookupCache::ClearCache(const LookupCacheWriteLockToken& lk) {
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// Clear L1 and L2 by clearing the full cache.
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FEXCore::Allocator::VirtualDontNeed(reinterpret_cast<void*>(PagePointer), TotalCacheSize, false);
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Shared->ClearCache(lk);
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}
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void GuestToHostMap::ClearCache(const LookupCacheWriteLockToken&) {
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// Allocate a new pointer from the BlockLinks pma again.
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BlockLinks = BlockLinks_pma->new_object<BlockLinksMapType>();
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// All code is gone, clear the block list
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BlockList.clear();
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}
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} // namespace FEXCore
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