Alyssa Rosenzweig 99854ff310 JIT: add GetZeroableReg helper ...

for inlining constant zeroes in applicable sources

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-02-24 15:54:49 -04:00

..

Config

Implement small TSC scaling

2024-02-20 12:05:44 -08:00

Context

Implement small TSC scaling

2024-02-20 12:05:44 -08:00

Core

JIT: add GetZeroableReg helper

2024-02-24 15:54:49 -04:00

GDBJIT

FEXCore/Interface/GDBJIT: Adds SPDX identifier

2023-09-19 17:33:15 -07:00

HLE/Thunks

Library Forwarding: Allocate packed arguments on the guest stack if needed

2024-02-05 18:10:34 +01:00

IR

IR: handle 8/16-bit AddNZCV/SubNZCV

2024-02-12 12:36:09 -04:00