Alyssa Rosenzweig 92f31648b9 RCLSE: optimize out pointless stores ...

can help a lot of x86 code because x86 is 2-address and a64 is 3-address, so x86
ends up with piles of movs that end up dead after translation

It's not a win across the board because our RA isn't aware of tied registers so
sometimes we regress moves. But it's a win on average, and the RA bits can be
improved with time.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-03-11 18:41:23 -04:00

..

Config

Implement small TSC scaling

2024-02-20 12:05:44 -08:00

Context

Implement small TSC scaling

2024-02-20 12:05:44 -08:00

Core

JIT: fix sha256msg1 encoding

2024-03-11 18:41:23 -04:00

GDBJIT

FEXCore/Interface/GDBJIT: Adds SPDX identifier

2023-09-19 17:33:15 -07:00

HLE/Thunks

Library Forwarding: Allocate packed arguments on the guest stack if needed

2024-02-05 18:10:34 +01:00

IR

RCLSE: optimize out pointless stores

2024-03-11 18:41:23 -04:00