Alyssa Rosenzweig 7a0119b092 OpcodeDispatcher: Optimize right shifts ...

Same technique as the left shifts. Gets rid of all our COND_FLAG_SET
use, which is good because it's a performance footgun.

Overall saves 17 instructions (!!!!) from the flag calculation code for
`sar eax, cl`.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2023-08-02 14:45:44 -04:00

..

Config

FEXCore: Remove erroneous asserts in the project

2023-07-28 13:36:05 -07:00

Context

Context: Make BackendFeatures public

2023-08-02 12:38:00 -04:00

Core

OpcodeDispatcher: Optimize right shifts

2023-08-02 14:45:44 -04:00

GDBJIT

SourcecodeResolver: Convert string to fextl

2023-03-16 03:21:45 -07:00

HLE/Thunks

Thunks: Mostly reverts #2672

2023-05-18 15:50:55 -07:00

IR

IR: Add TEST opcode

2023-08-02 12:38:00 -04:00