Ryan Houdek 4be649c44e OpcodeDispatcher: Optimizes < 32-bit register push ...

We don't need zero in the upper bits for a push.
Makes a couple variants optimal.

Adds missing tests to the 32-bit file, since only 32-bit can push a
32-bit register.

2023-10-10 12:04:41 -07:00

..

Config

FEXCore: Implements support for RPRES

2023-10-07 23:13:47 -07:00

Context

InstCountCI: Support multiple instructions in the tests

2023-10-09 21:49:53 -07:00

Core

OpcodeDispatcher: Optimizes < 32-bit register push

2023-10-10 12:04:41 -07:00

GDBJIT

FEXCore/Interface/GDBJIT: Adds SPDX identifier

2023-09-19 17:33:15 -07:00

HLE/Thunks

FEXCore/Interface/Thunks: Adds SPDX identifier

2023-09-19 17:33:14 -07:00

IR

IR: Adds scalar vector insert operations

2023-10-10 03:17:19 -07:00