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Ryan Houdek
8d28a441ab
This is a very minor performance change. On Cortex CPUs that support SVE, they do movprfx+<instruction> fusion to remove two cycles and a dependency from the backend. This is a minor win to convert from ASIMD mov+bsl to SVE movprfx+bsl because of this, saving two cycles and a dependency on Cortex A710 and A715. This is slightly less of a win on Cortex-A720/A725 because it supports zero-cycle vector register renames, but it is still a win on Cortex-X925 because that is an older core design that doesn't support zero-cycle vector register renames. Very silly little thing.