mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 10:00:16 +02:00
398 lines
9.8 KiB
JSON
398 lines
9.8 KiB
JSON
{
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"Features": {
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"Bitness": 32,
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"EnabledHostFeatures": [],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"FlagM",
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"FlagM2"
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]
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},
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"Instructions": {
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"push es": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x06",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #144]",
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"str w20, [x8, #-4]!"
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]
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},
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"pop es": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x07",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"add x8, x8, #0x4 (4)",
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"strh w20, [x28, #144]",
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"ubfx w20, w20, #3, #13",
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"add x0, x28, x20, lsl #2",
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"ldr w20, [x0, #896]",
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"str w20, [x28, #160]"
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]
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},
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"push cs": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x0e",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #146]",
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"str w20, [x8, #-4]!"
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]
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},
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"push ss": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x16",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #148]",
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"str w20, [x8, #-4]!"
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]
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},
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"pop ss": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x17",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"add x8, x8, #0x4 (4)",
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"strh w20, [x28, #148]",
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"ubfx w20, w20, #3, #13",
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"add x0, x28, x20, lsl #2",
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"ldr w20, [x0, #896]",
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"str w20, [x28, #168]"
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]
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},
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"push ds": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x1e",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #150]",
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"str w20, [x8, #-4]!"
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]
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},
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"pop ds": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x1f",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"add x8, x8, #0x4 (4)",
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"strh w20, [x28, #150]",
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"ubfx w20, w20, #3, #13",
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"add x0, x28, x20, lsl #2",
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"ldr w20, [x0, #896]",
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"str w20, [x28, #172]"
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]
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},
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"daa": {
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"ExpectedInstructionCount": 23,
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"Comment": "0x27",
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"ExpectedArm64ASM": [
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"uxtb w20, w4",
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"cset w21, hs",
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"and x22, x20, #0xf",
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"cmp x22, #0x9 (9)",
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"cset x22, hi",
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"eor w23, w27, w26",
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"ubfx w23, w23, #4, #1",
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"orr x22, x23, x22",
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"cmp x20, #0x99 (153)",
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"cset x23, hi",
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"orr x21, x21, x23",
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"add x23, x20, #0x6 (6)",
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"cmp x22, #0x0 (0)",
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"csel x20, x23, x20, ne",
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"add x23, x20, #0x60 (96)",
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"cmp x21, #0x0 (0)",
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"csel x26, x23, x20, ne",
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"bfxil w4, w26, #0, #8",
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"cmn wzr, w26, lsl #24",
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"mrs x20, nzcv",
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"orr w20, w20, w21, lsl #29",
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"eor w27, w26, w22, lsl #4",
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"msr nzcv, x20"
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]
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},
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"das": {
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"ExpectedInstructionCount": 26,
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"Comment": "0x2f",
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"ExpectedArm64ASM": [
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"uxtb w20, w4",
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"cset w21, hs",
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"and x22, x20, #0xf",
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"cmp x22, #0x9 (9)",
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"cset x22, hi",
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"eor w23, w27, w26",
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"ubfx w23, w23, #4, #1",
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"orr x22, x23, x22",
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"cmp x20, #0x99 (153)",
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"cset x23, hi",
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"orr x21, x21, x23",
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"cmp x20, #0x6 (6)",
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"csel x23, x22, x21, lo",
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"orr w23, w21, w23",
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"sub x24, x20, #0x6 (6)",
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"cmp x22, #0x0 (0)",
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"csel x20, x24, x20, ne",
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"sub x24, x20, #0x60 (96)",
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"cmp x21, #0x0 (0)",
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"csel x26, x24, x20, ne",
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"bfxil w4, w26, #0, #8",
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"cmn wzr, w26, lsl #24",
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"mrs x20, nzcv",
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"orr w20, w20, w23, lsl #29",
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"eor w27, w26, w22, lsl #4",
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"msr nzcv, x20"
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]
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},
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"aaa": {
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"ExpectedInstructionCount": 14,
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"Comment": "0x37",
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"ExpectedArm64ASM": [
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"and x20, x4, #0xf",
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"cmp x20, #0x9 (9)",
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"cset x20, hi",
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"eor w21, w27, w26",
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"ubfx w21, w21, #4, #1",
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"orr x20, x21, x20",
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"lsl x21, x20, #29",
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"eor w27, w26, w20, lsl #4",
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"msr nzcv, x21",
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"add w20, w4, #0x106 (262)",
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"csel w20, w20, w4, hs",
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"mov w21, #0xff0f",
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"and w20, w20, w21",
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"bfxil w4, w20, #0, #16"
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]
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},
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"aas": {
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"ExpectedInstructionCount": 14,
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"Comment": "0x3f",
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"ExpectedArm64ASM": [
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"and x20, x4, #0xf",
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"cmp x20, #0x9 (9)",
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"cset x20, hi",
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"eor w21, w27, w26",
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"ubfx w21, w21, #4, #1",
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"orr x20, x21, x20",
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"lsl x21, x20, #29",
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"eor w27, w26, w20, lsl #4",
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"msr nzcv, x21",
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"sub w20, w4, #0x106 (262)",
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"csel w20, w20, w4, hs",
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"mov w21, #0xff0f",
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"and w20, w20, w21",
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"bfxil w4, w20, #0, #16"
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]
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},
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"inc ax": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x40",
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"ExpectedArm64ASM": [
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"mov w20, #0x1",
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"uxth w27, w4",
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"cset w21, hs",
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"lsl w0, w27, #16",
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"cmn w0, w20, lsl #16",
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"add w26, w27, #0x1 (1)",
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"mrs x20, nzcv",
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"bfi w20, w21, #29, #1",
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"bfxil w4, w26, #0, #16",
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"msr nzcv, x20"
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]
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},
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"inc eax": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x40",
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"ExpectedArm64ASM": [
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"cset w20, hs",
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"mov x27, x4",
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"adds w26, w4, #0x1 (1)",
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"mrs x21, nzcv",
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"bfi w21, w20, #29, #1",
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"mov x4, x26",
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"msr nzcv, x21"
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]
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},
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"dec ax": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x48",
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"ExpectedArm64ASM": [
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"mov w20, #0x1",
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"uxth w27, w4",
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"cset w21, hs",
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"lsl w0, w27, #16",
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"cmp w0, w20, lsl #16",
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"sub w26, w27, #0x1 (1)",
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"mrs x20, nzcv",
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"bfi w20, w21, #29, #1",
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"bfxil w4, w26, #0, #16",
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"msr nzcv, x20"
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]
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},
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"push ax": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x50",
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"ExpectedArm64ASM": [
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"strh w4, [x8, #-2]!"
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]
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},
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"push eax": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x50",
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"ExpectedArm64ASM": [
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"str w4, [x8, #-4]!"
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]
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},
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"dec eax": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x48",
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"ExpectedArm64ASM": [
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"cset w20, hs",
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"mov x27, x4",
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"subs w26, w4, #0x1 (1)",
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"mrs x21, nzcv",
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"bfi w21, w20, #29, #1",
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"mov x4, x26",
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"msr nzcv, x21"
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]
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},
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"pusha": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x60",
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"ExpectedArm64ASM": [
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"mov w20, w8",
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"str w4, [x20, #-4]!",
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"str w5, [x20, #-4]!",
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"str w6, [x20, #-4]!",
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"str w7, [x20, #-4]!",
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"str w8, [x20, #-4]!",
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"str w9, [x20, #-4]!",
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"str w10, [x20, #-4]!",
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"mov w8, w20",
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"str w11, [x8, #-4]!"
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]
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},
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"pushad": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x60",
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"ExpectedArm64ASM": [
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"mov w20, w8",
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"str w4, [x20, #-4]!",
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"str w5, [x20, #-4]!",
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"str w6, [x20, #-4]!",
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"str w7, [x20, #-4]!",
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"str w8, [x20, #-4]!",
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"str w9, [x20, #-4]!",
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"str w10, [x20, #-4]!",
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"mov w8, w20",
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"str w11, [x8, #-4]!"
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]
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},
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"popa": {
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"ExpectedInstructionCount": 14,
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"Comment": "0x61",
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"ExpectedArm64ASM": [
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"ldr w11, [x8]",
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"add x20, x8, #0x4 (4)",
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"ldr w10, [x20]",
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"add x20, x20, #0x4 (4)",
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"ldr w9, [x20]",
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"add x20, x20, #0x8 (8)",
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"ldr w7, [x20]",
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"add x20, x20, #0x4 (4)",
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"ldr w6, [x20]",
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"add x20, x20, #0x4 (4)",
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"ldr w5, [x20]",
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"add x20, x20, #0x4 (4)",
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"ldr w4, [x20]",
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"add x8, x20, #0x4 (4)"
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]
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},
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"popad": {
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"ExpectedInstructionCount": 14,
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"Comment": "0x61",
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"ExpectedArm64ASM": [
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"ldr w11, [x8]",
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"add x20, x8, #0x4 (4)",
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"ldr w10, [x20]",
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"add x20, x20, #0x4 (4)",
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"ldr w9, [x20]",
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"add x20, x20, #0x8 (8)",
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"ldr w7, [x20]",
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"add x20, x20, #0x4 (4)",
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"ldr w6, [x20]",
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"add x20, x20, #0x4 (4)",
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"ldr w5, [x20]",
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"add x20, x20, #0x4 (4)",
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"ldr w4, [x20]",
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"add x8, x20, #0x4 (4)"
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]
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},
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"aam": {
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"ExpectedInstructionCount": 8,
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"Comment": "0xd4",
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"ExpectedArm64ASM": [
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"uxtb w20, w4",
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"mov w21, #0xa",
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"udiv x22, x20, x21",
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"udiv x2, x20, x21",
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"msub x20, x2, x21, x20",
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"add x26, x20, x22, lsl #8",
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"bfxil w4, w26, #0, #16",
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"cmn wzr, w26, lsl #24"
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]
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},
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"aad": {
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"ExpectedInstructionCount": 7,
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"Comment": "0xd5",
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"ExpectedArm64ASM": [
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"lsr w20, w4, #8",
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"mov w21, #0xa",
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"mul x20, x20, x21",
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"add x20, x4, x20",
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"and x26, x20, #0xff",
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"bfxil w4, w26, #0, #16",
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"cmn wzr, w26, lsl #24"
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]
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},
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"db 0xd4, 0x40": {
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"ExpectedInstructionCount": 8,
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"Comment": [
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"aam with a different immediate byte base",
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"0xd4"
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],
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"ExpectedArm64ASM": [
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"uxtb w20, w4",
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"mov w21, #0x40",
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"udiv x22, x20, x21",
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"udiv x2, x20, x21",
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"msub x20, x2, x21, x20",
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"add x26, x20, x22, lsl #8",
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"bfxil w4, w26, #0, #16",
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"cmn wzr, w26, lsl #24"
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]
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},
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"db 0xd5, 0x40": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"aad with a different immediate byte base",
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"0xd5"
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],
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"ExpectedArm64ASM": [
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"lsr w20, w4, #8",
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"lsl x20, x20, #6",
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"add x20, x4, x20",
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"and x26, x20, #0xff",
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"bfxil w4, w26, #0, #16",
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"cmn wzr, w26, lsl #24"
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]
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},
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"salc": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xd6",
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"ExpectedArm64ASM": [
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"csetm w20, hs",
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"bfxil w4, w20, #0, #8"
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]
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}
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}
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}
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