mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 23:00:17 +02:00
Ryan Houdek
40cad15da9
Argumentless IR emitter functions were prone to generating invalid code. Remove them from the python emitter and change the branch instructions that were using them to a new version instead. Adds NumUse tracking as well.
334 lines
12 KiB
C++
334 lines
12 KiB
C++
#pragma once
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/Debug/X86Tables.h>
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#include <FEXCore/IR/IR.h>
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#include <cstdint>
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#include <functional>
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namespace FEXCore::IR {
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class Pass;
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class PassManager;
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class OpDispatchBuilder final {
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friend class FEXCore::IR::Pass;
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friend class FEXCore::IR::PassManager;
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public:
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struct {
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bool HadUnconditionalExit {false};
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} Information;
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bool ShouldDump {false};
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OpDispatchBuilder();
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IRListView<false> ViewIR() { return IRListView<false>(&Data, &ListData); }
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IRListView<true> *CreateIRCopy() { return new IRListView<true>(&Data, &ListData); }
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void ResetWorkingList();
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bool HadDecodeFailure() { return DecodeFailure; }
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void BeginBlock();
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void EndBlock(uint64_t RIPIncrement);
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void ExitFunction();
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// Dispatch builder functions
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#define OpcodeArgs [[maybe_unused]] FEXCore::X86Tables::DecodedOp Op
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void UnhandledOp(OpcodeArgs);
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void MOVOp(OpcodeArgs);
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void ALUOp(OpcodeArgs);
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void INTOp(OpcodeArgs);
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void SyscallOp(OpcodeArgs);
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void LEAOp(OpcodeArgs);
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void NOPOp(OpcodeArgs);
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void RETOp(OpcodeArgs);
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void SecondaryALUOp(OpcodeArgs);
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void ADCOp(OpcodeArgs);
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void SBBOp(OpcodeArgs);
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void PUSHOp(OpcodeArgs);
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void POPOp(OpcodeArgs);
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void LEAVEOp(OpcodeArgs);
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void CALLOp(OpcodeArgs);
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void CALLAbsoluteOp(OpcodeArgs);
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void CondJUMPOp(OpcodeArgs);
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void JUMPOp(OpcodeArgs);
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void JUMPAbsoluteOp(OpcodeArgs);
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void TESTOp(OpcodeArgs);
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void MOVSXDOp(OpcodeArgs);
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void MOVSXOp(OpcodeArgs);
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void MOVZXOp(OpcodeArgs);
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void CMPOp(OpcodeArgs);
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void SETccOp(OpcodeArgs);
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void CQOOp(OpcodeArgs);
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void CDQOp(OpcodeArgs);
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void XCHGOp(OpcodeArgs);
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void SAHFOp(OpcodeArgs);
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void LAHFOp(OpcodeArgs);
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void MOVSegOp(OpcodeArgs);
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void FLAGControlOp(OpcodeArgs);
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void MOVOffsetOp(OpcodeArgs);
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void CMOVOp(OpcodeArgs);
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void CPUIDOp(OpcodeArgs);
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void SHLOp(OpcodeArgs);
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void SHROp(OpcodeArgs);
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void ASHROp(OpcodeArgs);
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void ROROp(OpcodeArgs);
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void ROLOp(OpcodeArgs);
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void BTOp(OpcodeArgs);
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void IMUL1SrcOp(OpcodeArgs);
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void IMUL2SrcOp(OpcodeArgs);
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void IMULOp(OpcodeArgs);
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void STOSOp(OpcodeArgs);
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void MOVSOp(OpcodeArgs);
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void CMPSOp(OpcodeArgs);
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void BSWAPOp(OpcodeArgs);
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void RDTSCOp(OpcodeArgs);
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void INCOp(OpcodeArgs);
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void DECOp(OpcodeArgs);
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void NEGOp(OpcodeArgs);
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void DIVOp(OpcodeArgs);
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void IDIVOp(OpcodeArgs);
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void BSFOp(OpcodeArgs);
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void BSROp(OpcodeArgs);
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void CMPXCHGOp(OpcodeArgs);
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void MULOp(OpcodeArgs);
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void NOTOp(OpcodeArgs);
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// SSE
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void MOVUPSOp(OpcodeArgs);
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void MOVLHPSOp(OpcodeArgs);
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void MOVHPDOp(OpcodeArgs);
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void VectorALUOp(OpcodeArgs);
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void MOVQOp(OpcodeArgs);
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void PADDQOp(OpcodeArgs);
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void PSUBQOp(OpcodeArgs);
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template<size_t ElementSize>
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void PMINUOp(OpcodeArgs);
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void PMINSWOp(OpcodeArgs);
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void PMOVMSKBOp(OpcodeArgs);
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void PUNPCKLOp(OpcodeArgs);
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void PUNPCKHOp(OpcodeArgs);
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template<size_t ElementSize, bool Low>
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void PSHUFDOp(OpcodeArgs);
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void PCMPEQOp(OpcodeArgs);
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template<size_t ElementSize>
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void PCMPGTOp(OpcodeArgs);
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void MOVDOp(OpcodeArgs);
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template<size_t ElementSize>
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void PSRLD(OpcodeArgs);
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template<size_t ElementSize, bool Scalar>
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void PSLL(OpcodeArgs);
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void PSRLDQ(OpcodeArgs);
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void MOVDDUPOp(OpcodeArgs);
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template<size_t ElementSize>
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void SHUFOp(OpcodeArgs);
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#undef OpcodeArgs
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/**
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* @name IR allocation routines
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*
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* @{ */
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// These handlers add cost to the constructor and destructor
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// If it becomes an issue then blow them away
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// GCC also generates some pretty atrocious code around these
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// Use Clang!
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#define IROP_ALLOCATE_HELPERS
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#define IROP_DISPATCH_HELPERS
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#include "IRDefines.inc"
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IRPair<IROp_Constant> _Constant(uint8_t Size, uint64_t Constant) {
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auto Op = AllocateOp<IROp_Constant, IROps::OP_CONSTANT>();
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Op.first->Constant = Constant;
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Op.first->Header.Size = Size / 8;
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Op.first->Header.Elements = 1;
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Op.first->Header.NumArgs = 0;
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Op.first->Header.HasDest = true;
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return Op;
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}
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IRPair<IROp_Bfe> _Bfe(uint8_t Width, uint8_t lsb, OrderedNode *ssa0) {
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return _Bfe(ssa0, Width, lsb);
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}
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IRPair<IROp_Bfi> _Bfi(uint8_t Width, uint8_t lsb, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _Bfi(ssa0, ssa1, Width, lsb);
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}
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IRPair<IROp_StoreMem> _StoreMem(uint8_t Size, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _StoreMem(ssa0, ssa1, Size);
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}
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IRPair<IROp_LoadMem> _LoadMem(uint8_t Size, OrderedNode *ssa0) {
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return _LoadMem(ssa0, Size);
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}
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IRPair<IROp_StoreContext> _StoreContext(uint8_t Size, uint32_t Offset, OrderedNode *ssa0) {
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return _StoreContext(ssa0, Size, Offset);
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}
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IRPair<IROp_Select> _Select(uint8_t Cond, OrderedNode *ssa0, OrderedNode *ssa1, OrderedNode *ssa2, OrderedNode *ssa3) {
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return _Select(ssa0, ssa1, ssa2, ssa3, Cond);
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}
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IRPair<IROp_Sext> _Sext(uint8_t Size, OrderedNode *ssa0) {
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return _Sext(ssa0, Size);
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}
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IRPair<IROp_Zext> _Zext(uint8_t Size, OrderedNode *ssa0) {
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return _Zext(ssa0, Size);
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}
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IRPair<IROp_VInsElement> _VInsElement(uint8_t RegisterSize, uint8_t ElementSize, uint8_t DestIdx, uint8_t SrcIdx, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VInsElement(ssa0, ssa1, RegisterSize, ElementSize, DestIdx, SrcIdx);
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}
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IRPair<IROp_VAdd> _VAdd(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VAdd(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VSub> _VSub(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VSub(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VUMin> _VUMin(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VUMin(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VSMin> _VSMin(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VSMin(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VZip> _VZip(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VZip(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VZip2> _VZip2(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VZip2(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VCMPEQ> _VCMPEQ(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VCMPEQ(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VCMPGT> _VCMPGT(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VCMPGT(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VUShl> _VUShl(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VUShl(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VUShlS> _VUShlS(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VUShlS(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_VUShr> _VUShr(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) {
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return _VUShr(ssa0, ssa1, RegisterSize, ElementSize);
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}
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IRPair<IROp_Jump> _Jump() {
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return _Jump(InvalidNode);
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}
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IRPair<IROp_CondJump> _CondJump(OrderedNode *ssa0) {
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return _CondJump(ssa0, InvalidNode);
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}
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void SetJumpTarget(IRPair<IROp_Jump> Op, OrderedNode *Target) {
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Op.first->Header.Args[0].NodeOffset = Target->Wrapped(ListData.Begin()).NodeOffset;
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}
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void SetJumpTarget(IRPair<IROp_CondJump> Op, OrderedNode *Target) {
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Op.first->Header.Args[1].NodeOffset = Target->Wrapped(ListData.Begin()).NodeOffset;
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}
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/** @} */
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bool IsValueConstant(NodeWrapper ssa, uint64_t *Constant) {
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OrderedNode *RealNode = reinterpret_cast<OrderedNode*>(ssa.GetPtr(ListData.Begin()));
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FEXCore::IR::IROp_Header *IROp = RealNode->Op(Data.Begin());
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if (IROp->Op == OP_CONSTANT) {
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auto Op = IROp->C<IR::IROp_Constant>();
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*Constant = Op->Constant;
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return true;
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}
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return false;
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}
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// This is fairly special in how it operates
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// Since the node is decoupled from the backing op then we can swap out the backing op without much overhead
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// This can potentially cause problems where multiple nodes are pointing to the same IROp
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OrderedNode *ReplaceAllUsesWith(OrderedNode *Node, IROp_Header *Op) {
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Node->Header.Value.SetOffset(Data.Begin(), reinterpret_cast<uintptr_t>(Op));
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return Node;
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}
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// This is similar to the previous op except that we pass in a node
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// This takes the op backing in the new node and replaces the node in the other node
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// Again can cause problems where things are pointing to NewNode and haven't been decoupled
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OrderedNode *ReplaceAllUsesWith(OrderedNode *Node, OrderedNode *NewNode) {
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Node->Header.Value.NodeOffset = NewNode->Header.Value.NodeOffset;
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return Node;
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}
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void Unlink(OrderedNode *Node) {
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Node->Unlink(ListData.Begin());
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}
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void SetPackedRFLAG(bool Lower8, OrderedNode *Src);
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OrderedNode *GetPackedRFLAG(bool Lower8);
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void CopyData(OpDispatchBuilder const &rhs) {
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LogMan::Throw::A(rhs.Data.BackingSize() <= Data.BackingSize(), "Trying to take ownership of data that is too large");
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LogMan::Throw::A(rhs.ListData.BackingSize() <= ListData.BackingSize(), "Trying to take ownership of data that is too large");
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Data.CopyData(rhs.Data);
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ListData.CopyData(rhs.ListData);
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}
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private:
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void TestFunction();
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bool DecodeFailure{false};
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OrderedNode *LoadSource(FEXCore::X86Tables::DecodedOp const& Op, FEXCore::X86Tables::DecodedOperand const& Operand, uint32_t Flags, bool LoadData = true, bool ForceLoad = false);
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OrderedNode *LoadSource_WithOpSize(FEXCore::X86Tables::DecodedOp const& Op, FEXCore::X86Tables::DecodedOperand const& Operand, uint8_t OpSize, uint32_t Flags, bool LoadData = true, bool ForceLoad = false);
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void StoreResult_WithOpSize(FEXCore::X86Tables::DecodedOp Op, FEXCore::X86Tables::DecodedOperand const& Operand, OrderedNode *const Src, uint8_t OpSize);
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void StoreResult(FEXCore::X86Tables::DecodedOp Op, FEXCore::X86Tables::DecodedOperand const& Operand, OrderedNode *const Src);
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void StoreResult(FEXCore::X86Tables::DecodedOp Op, OrderedNode *const Src);
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uint8_t GetDstSize(FEXCore::X86Tables::DecodedOp Op);
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uint8_t GetSrcSize(FEXCore::X86Tables::DecodedOp Op);
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template<unsigned BitOffset>
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void SetRFLAG(OrderedNode *Value);
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void SetRFLAG(OrderedNode *Value, unsigned BitOffset);
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OrderedNode *GetRFLAG(unsigned BitOffset);
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void GenerateFlags_ADC(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
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void GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
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void GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
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void GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
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void GenerateFlags_MUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *High);
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void GenerateFlags_UMUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *High);
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void GenerateFlags_Logical(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
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void GenerateFlags_Rotate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
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OrderedNode *CreateNode(IROp_Header *Op) {
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uintptr_t ListBegin = ListData.Begin();
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size_t Size = sizeof(OrderedNode);
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void *Ptr = ListData.Allocate(Size);
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OrderedNode *Node = new (Ptr) OrderedNode();
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Node->Header.Value.SetOffset(Data.Begin(), reinterpret_cast<uintptr_t>(Op));
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if (CurrentWriteCursor) {
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CurrentWriteCursor->append(ListBegin, Node);
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}
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CurrentWriteCursor = Node;
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return Node;
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}
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void SetWriteCursor(OrderedNode *Node) {
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CurrentWriteCursor = Node;
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}
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OrderedNode *GetWriteCursor() {
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return CurrentWriteCursor;
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}
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OrderedNode *CurrentWriteCursor = nullptr;
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// These could be combined with a little bit of work to be more efficient with memory usage. Isn't a big deal
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IntrusiveAllocator Data;
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IntrusiveAllocator ListData;
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OrderedNode *InvalidNode;
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};
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void InstallOpcodeHandlers();
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}
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