steam-frame/FEX-Emu--FEX
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88fee019a1535737dd7aa8b00d4ad2fa413a3c19
FEX-Emu--FEX/External/FEXCore/Source/Interface/IR
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Lioncache acbfee55b4 IR: Allow provising register size for VBSL 
Necessary, since this will now be used with both 256-bit and 128-bit
registers, rather than just 128-bit.
2023-02-06 23:04:26 -05:00
..
Passes
JIT: Adds a JIT data header and tail.
2023-02-06 14:06:37 -08:00
AOTIR.cpp
Misc: Convert assert logs to assume+assert that can be
2022-07-17 12:51:43 -07:00
AOTIR.h
GDBSymbols: Add gdb reader for fex, GDBSymbols option to enable
2022-06-24 16:27:16 +03:00
IR.json
IR: Allow provising register size for VBSL
2023-02-06 23:04:26 -05:00
IRDumper.cpp
IR: Remove HasDest member
2023-01-08 17:57:47 -08:00
IREmitter.cpp
IR: Removes NumArgs member from IR ops
2023-01-30 11:53:05 -08:00
IRParser.cpp
unittests/IR: Update tests for new IR semantics
2022-11-22 23:06:18 -08:00
Passes.h
Passes: Remove StaticRegisterAllocation pass
2022-11-22 21:06:58 -08:00
PassManager.cpp
Passes: Remove StaticRegisterAllocation pass
2022-11-22 21:06:58 -08:00
PassManager.h
CoreState: Use a union for representing xmm data
2022-07-26 16:56:54 -04:00