mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 21:00:17 +02:00
esullivan
8cc967fa22
This change avoids using the LDAPUR instruction with CPUs that are know to be impacted by an ARM CPU errata that results in poor performance.
670 lines
14 KiB
C++
670 lines
14 KiB
C++
// SPDX-License-Identifier: MIT
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#pragma once
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#include <FEXCore/Core/HostFeatures.h>
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#include <FEXCore/Utils/EnumUtils.h>
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#include <cstddef>
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namespace FEX {
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class CPUFeatures {
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public:
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class FeatureReg {
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public:
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void SetReg(uint64_t _Reg) {
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Reg = _Reg;
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}
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uint64_t Get() const {
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return Reg;
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}
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protected:
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// All feature flag fields are 4-bits.
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uint64_t GetField(uint64_t Offset) const {
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return (Reg >> Offset) & 0b1111;
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}
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uint64_t Reg {};
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};
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enum class Feature : uint32_t {
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// ISAR0
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AES,
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PMULL,
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SHA1,
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SHA2,
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SHA512,
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CRC32,
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LSE,
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LSE128,
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TME,
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RDM,
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SHA3,
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SM3,
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SM4,
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DotProd,
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FlagM,
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FlagM2,
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RNDR,
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// PFR0
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FP,
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FP16,
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ASIMD,
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ASIMD16,
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RAS,
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SVE,
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DIT,
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CSV2,
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CSV3,
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// PFR1
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BTI,
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SSBS,
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SSBS2,
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MTE,
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MTE2,
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MTE3,
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SME,
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SME2,
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// ISAR1
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DPB,
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DPB2,
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JSCVT,
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FCMA,
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LRCPC,
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LRCPC2,
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LRCPC3,
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FRINTTS,
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SB,
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SPECRES,
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SPECRES2,
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BF16,
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SME_F64F64,
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I8MM,
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XS,
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LS64,
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LS64_V,
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LS64_ACCDATA,
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// MMFR0
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ECV,
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// MMFR2
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LSE2,
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// ZFR0
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SVE2,
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SVE2_1,
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SVE_AES,
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SVE_PMULL128,
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SVE_BitPerm,
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SVE_BF16,
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SVE_B16B16,
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SVE_SHA3,
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SVE_SM4,
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SVE_I8MM,
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SVE_F32MM,
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SVE_F64MM,
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// MMFR1
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AFP,
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// ISAR2
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WFxt,
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RPRES,
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PACQARMA3,
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MOPS,
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HBC,
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CLRBHB,
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SYSREG128,
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SYSINSTR128,
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PRFMSLC,
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RPRFM,
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CSSC,
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// Max indicator
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MAX,
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};
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class DCZIDReg final : public FeatureReg {
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public:
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bool SupportsDCZVA() const {
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return (Reg & DCZID_DZP_MASK) == 0;
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}
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uint32_t BlockSizeInBytes() const {
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uint32_t DCZID_Log2 = Reg & DCZID_BS_MASK;
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return (1 << DCZID_Log2) * sizeof(uint32_t);
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}
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private:
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// Data Zero Prohibited flag
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// 0b0 = ZVA/GVA/GZVA permitted
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// 0b1 = ZVA/GVA/GZVA prohibited
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[[maybe_unused]] constexpr static uint32_t DCZID_DZP_MASK = 0b1'0000;
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// Log2 of the blocksize in 32-bit words
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[[maybe_unused]] constexpr static uint32_t DCZID_BS_MASK = 0b0'1111;
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};
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// This list is informed by Linux kernel's `Documentation/arch/arm64/cpu-feature-registers.rst`
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enum class FeatureRegType {
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ISAR0_EL1,
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PFR0_EL1,
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PFR1_EL1,
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MIDR_EL1,
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ISAR1_EL1,
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MMFR0_EL1,
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MMFR2_EL1,
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ZFR0_EL1,
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MMFR1_EL1,
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ISAR2_EL1,
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};
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#define FIELD_FETCHER(feature, field, minimum_field) \
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bool Supports##feature() const { \
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return GetField(field) >= minimum_field; \
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}
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class ISAR0Reg final : public FeatureReg {
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public:
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FIELD_FETCHER(AES, AES, 0b0001);
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FIELD_FETCHER(PMULL, AES, 0b0010);
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FIELD_FETCHER(SHA1, SHA1, 0b0001);
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FIELD_FETCHER(SHA2, SHA2, 0b0001);
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FIELD_FETCHER(SHA512, SHA2, 0b0010);
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FIELD_FETCHER(CRC32, CRC32, 0b0001);
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FIELD_FETCHER(LSE, Atomic, 0b0010);
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FIELD_FETCHER(LSE128, Atomic, 0b0011);
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FIELD_FETCHER(TME, TME, 0b0001);
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FIELD_FETCHER(RDM, RDM, 0b0001);
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FIELD_FETCHER(SHA3, SHA3, 0b0001);
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FIELD_FETCHER(SM3, SM3, 0b0001);
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FIELD_FETCHER(SM4, SM4, 0b0001);
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FIELD_FETCHER(DotProd, DP, 0b0001);
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FIELD_FETCHER(FHM, FHM, 0b0001);
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FIELD_FETCHER(FlagM, TS, 0b0001);
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FIELD_FETCHER(FlagM2, TS, 0b0010);
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FIELD_FETCHER(TLBIOS, TLB, 0b0001);
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FIELD_FETCHER(TLBIRANGE, TLB, 0b0010);
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FIELD_FETCHER(RNDR, RNDR, 0b0001);
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private:
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enum Field {
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RES0 = 0 * 4,
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AES = 1 * 4,
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SHA1 = 2 * 4,
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SHA2 = 3 * 4,
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CRC32 = 4 * 4,
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Atomic = 5 * 4,
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TME = 6 * 4,
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RDM = 7 * 4,
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SHA3 = 8 * 4,
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SM3 = 9 * 4,
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SM4 = 10 * 4,
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DP = 11 * 4,
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FHM = 12 * 4,
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TS = 13 * 4,
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TLB = 14 * 4,
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RNDR = 15 * 4,
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};
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};
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class PFR0Reg final : public FeatureReg {
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public:
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FIELD_FETCHER(AA64_EL0, EL0, 0b0001);
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FIELD_FETCHER(AA32_EL0, EL0, 0b0010);
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FIELD_FETCHER(AA64_EL1, EL1, 0b0001);
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FIELD_FETCHER(AA32_EL1, EL1, 0b0010);
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FIELD_FETCHER(AA64_EL2, EL2, 0b0001);
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FIELD_FETCHER(AA32_EL2, EL2, 0b0010);
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FIELD_FETCHER(AA64_EL3, EL3, 0b0001);
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FIELD_FETCHER(AA32_EL3, EL3, 0b0010);
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bool SupportsFP() const {
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return GetField(FP) != 0b1111;
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}
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FIELD_FETCHER(HP, FP, 0b0001);
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bool SupportsAdvSIMD() const {
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return GetField(AdvSIMD) != 0b1111;
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}
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FIELD_FETCHER(ASIMDHP, AdvSIMD, 0b0001);
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FIELD_FETCHER(GIC4_0, GIC, 0b0001);
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FIELD_FETCHER(GIC4_1, GIC, 0b0011);
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FIELD_FETCHER(RAS, RAS, 0b0001);
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FIELD_FETCHER(RAS1_1, RAS, 0b0010);
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FIELD_FETCHER(RAS2, RAS, 0b0011);
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FIELD_FETCHER(SVE, SVE, 0b0001);
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FIELD_FETCHER(SEL2, SEL2, 0b0001);
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uint64_t MPAM_Major() const {
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return GetField(MPAM);
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}
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FIELD_FETCHER(AMU1, AMU, 0b0001);
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FIELD_FETCHER(AMU1_1, AMU, 0b0010);
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FIELD_FETCHER(DIT, DIT, 0b0001);
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FIELD_FETCHER(RME, RME, 0b0001);
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FIELD_FETCHER(CSV2, CSV2, 0b0001);
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FIELD_FETCHER(CSV2_2, CSV2, 0b0010);
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FIELD_FETCHER(CSV2_3, CSV2, 0b0011);
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FIELD_FETCHER(CSV3, CSV3, 0b0001);
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private:
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enum Field {
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EL0 = 0 * 4,
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EL1 = 1 * 4,
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EL2 = 2 * 4,
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EL3 = 3 * 4,
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FP = 4 * 4,
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AdvSIMD = 5 * 4,
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GIC = 6 * 4,
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RAS = 7 * 4,
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SVE = 8 * 4,
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SEL2 = 9 * 4,
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MPAM = 10 * 4,
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AMU = 11 * 4,
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DIT = 12 * 4,
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RME = 13 * 4,
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CSV2 = 14 * 4,
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CSV3 = 15 * 4,
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};
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};
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class PFR1Reg final : public FeatureReg {
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public:
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FIELD_FETCHER(BTI, BT, 0b0001);
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FIELD_FETCHER(SSBS, SSBS, 0b0001);
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FIELD_FETCHER(SSBS2, SSBS, 0b0010);
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FIELD_FETCHER(MTE, MTE, 0b0001);
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FIELD_FETCHER(MTE2, MTE, 0b0010);
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FIELD_FETCHER(MTE3, MTE, 0b0011);
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uint64_t RAS_Minor() const {
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return GetField(RAS_frac);
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}
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uint64_t MPAM_Minor() const {
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return GetField(MPAM_frac);
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}
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FIELD_FETCHER(SME, SME, 0b0001);
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FIELD_FETCHER(SME2, SME, 0b0010);
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FIELD_FETCHER(RNDR_trap, RNDR_trap, 0b0001);
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uint64_t CSV2_Minor() const {
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return GetField(CSV2_frac);
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}
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FIELD_FETCHER(NMI, NMI, 0b0001);
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uint64_t MTE_Minor() const {
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return GetField(MTE_frac);
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}
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FIELD_FETCHER(GCS, GCS, 0b0001);
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FIELD_FETCHER(THE, THE, 0b0001);
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FIELD_FETCHER(MTEX, MTEX, 0b0001);
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FIELD_FETCHER(DoubleFault2, DF2, 0b0001);
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FIELD_FETCHER(PFAR, PFAR, 0b0001);
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private:
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enum Field {
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BT = 0 * 4,
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SSBS = 1 * 4,
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MTE = 2 * 4,
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RAS_frac = 3 * 4,
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MPAM_frac = 4 * 4,
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RES0 = 5 * 4,
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SME = 6 * 4,
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RNDR_trap = 7 * 4,
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CSV2_frac = 8 * 4,
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NMI = 9 * 4,
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MTE_frac = 10 * 4,
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GCS = 11 * 4,
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THE = 12 * 4,
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MTEX = 13 * 4,
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DF2 = 14 * 4,
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PFAR = 15 * 4,
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};
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};
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class MIDRReg final : public FeatureReg {
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public:
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uint64_t GetRevision() const {
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return GetField(Revision);
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}
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uint64_t GetPartNum() const {
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return (Reg >> 4) & 0xFFF;
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}
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uint64_t GetArchitecture() const {
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return GetField(Architecture);
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}
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uint64_t GetVariant() const {
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return GetField(Variant);
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}
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uint64_t GetImplementer() const {
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return (Reg >> 24) & 0xFFFF;
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}
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private:
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enum Field {
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Revision = 0 * 4,
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// Partnum is 3 fields [15:4]
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Architecture = 4 * 4,
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Variant = 5 * 4,
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// Implementer is 2 fields [31:24]
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// Upper 32-bits is entirely reserved
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};
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};
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class ISAR1Reg final : public FeatureReg {
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public:
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FIELD_FETCHER(DPB, DPB, 0b0001);
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FIELD_FETCHER(DPB2, DPB, 0b0010);
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// Ignoring APA and API
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FIELD_FETCHER(JSCVT, JSCVT, 0b0001);
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FIELD_FETCHER(FCMA, FCMA, 0b0001);
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FIELD_FETCHER(LRCPC, LRCPC, 0b0001);
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FIELD_FETCHER(LRCPC2, LRCPC, 0b0010);
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FIELD_FETCHER(LRCPC3, LRCPC, 0b0011);
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// Ignoring GPA and GPI
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FIELD_FETCHER(FRINTTS, FRINTTS, 0b0001);
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FIELD_FETCHER(SB, SB, 0b0001);
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FIELD_FETCHER(SPECRES, SPECRES, 0b0001);
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FIELD_FETCHER(SPECRES2, SPECRES, 0b0010);
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FIELD_FETCHER(BF16, BF16, 0b0001);
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FIELD_FETCHER(SME_F64F64, BF16, 0b0010);
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FIELD_FETCHER(DGH, DGH, 0b0001);
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FIELD_FETCHER(I8MM, I8MM, 0b0001);
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FIELD_FETCHER(XS, XS, 0b0001);
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FIELD_FETCHER(LS64, LS64, 0b0001);
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FIELD_FETCHER(LS64_V, LS64, 0b0010);
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FIELD_FETCHER(LS64_ACCDATA, LS64, 0b0011);
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private:
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enum Field {
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DPB = 0 * 4,
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APA = 1 * 4,
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API = 2 * 4,
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JSCVT = 3 * 4,
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FCMA = 4 * 4,
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LRCPC = 5 * 4,
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GPA = 6 * 4,
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GPI = 7 * 4,
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FRINTTS = 8 * 4,
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SB = 9 * 4,
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SPECRES = 10 * 4,
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BF16 = 11 * 4,
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DGH = 12 * 4,
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I8MM = 13 * 4,
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XS = 14 * 4,
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LS64 = 15 * 4,
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};
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};
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class MMFR0Reg final : public FeatureReg {
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public:
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FIELD_FETCHER(ECV, ECV, 0b0010);
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private:
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enum Field {
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PARange = 0 * 4,
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ASIDBits = 1 * 4,
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BigEnd = 2 * 4,
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SNSMem = 3 * 4,
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BigEndEL0 = 4 * 4,
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TGran16 = 5 * 4,
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TGran64 = 6 * 4,
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TGran4 = 7 * 4,
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TGran16_2 = 8 * 4,
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TGran64_2 = 9 * 4,
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TGran4_2 = 10 * 4,
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ExS = 11 * 4,
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RES0 = 12 * 4,
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RES1 = 13 * 4,
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FGT = 14 * 4,
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ECV = 15 * 4,
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};
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};
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class MMFR2Reg final : public FeatureReg {
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public:
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FIELD_FETCHER(LSE2, AT, 0b0001);
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private:
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enum Field {
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CnP = 0 * 4,
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UAO = 1 * 4,
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LSM = 2 * 4,
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IESB = 3 * 4,
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VARange = 4 * 4,
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CCIDX = 5 * 4,
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NV = 6 * 4,
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ST = 7 * 4,
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AT = 8 * 4,
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IDS = 9 * 4,
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FWB = 10 * 4,
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RES0 = 11 * 4,
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TTL = 12 * 4,
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BBM = 13 * 4,
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EVT = 14 * 4,
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E0PD = 15 * 4,
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};
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};
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class ZFR0Reg final : public FeatureReg {
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public:
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FIELD_FETCHER(SVE2, SVEver, 0b0001);
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FIELD_FETCHER(SVE2_1, SVEver, 0b0010);
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FIELD_FETCHER(SVE_AES, AES, 0b0001);
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FIELD_FETCHER(SVE_PMULL128, AES, 0b0010);
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FIELD_FETCHER(SVE_BitPerm, BitPerm, 0b0001);
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FIELD_FETCHER(SVE_BF16, BF16, 0b0001);
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FIELD_FETCHER(SME_F64F64, BF16, 0b0010);
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FIELD_FETCHER(SVE_B16B16, B16B16, 0b0010);
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FIELD_FETCHER(SVE_SHA3, SHA3, 0b0001);
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FIELD_FETCHER(SVE_SM4, SM4, 0b0001);
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FIELD_FETCHER(SVE_I8MM, I8MM, 0b0001);
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FIELD_FETCHER(SVE_F32MM, F32MM, 0b0001);
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FIELD_FETCHER(SVE_F64MM, F64MM, 0b0001);
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private:
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enum Field {
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SVEver = 0 * 4,
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AES = 1 * 4,
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RES0 = 2 * 4,
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RES1 = 3 * 4,
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BitPerm = 4 * 4,
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BF16 = 5 * 4,
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B16B16 = 6 * 4,
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RES2 = 7 * 4,
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SHA3 = 8 * 4,
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RES3 = 9 * 4,
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SM4 = 10 * 4,
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I8MM = 11 * 4,
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RES4 = 12 * 4,
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F32MM = 13 * 4,
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F64MM = 14 * 4,
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RES5 = 15 * 4,
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};
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};
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class MMFR1Reg final : public FeatureReg {
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public:
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FIELD_FETCHER(AFP, AFP, 0b0001);
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private:
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enum Field {
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HAFDBS = 0 * 4,
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VMIDBits = 1 * 4,
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VH = 2 * 4,
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HPDS = 3 * 4,
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LO = 4 * 4,
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PAN = 5 * 4,
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SpecSEI = 6 * 4,
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XNX = 7 * 4,
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|
TWED = 8 * 4,
|
|
ETS = 9 * 4,
|
|
HCX = 10 * 4,
|
|
AFP = 11 * 4,
|
|
nTLBPA = 12 * 4,
|
|
TIDCP1 = 13 * 4,
|
|
CMOW = 14 * 4,
|
|
ECBHB = 15 * 4,
|
|
};
|
|
};
|
|
|
|
class ISAR2Reg final : public FeatureReg {
|
|
public:
|
|
FIELD_FETCHER(WFxt, WFxt, 0b0010);
|
|
|
|
FIELD_FETCHER(RPRES, RPRES, 0b0001);
|
|
|
|
FIELD_FETCHER(PACQARMA3, GPA3, 0b0001);
|
|
|
|
FIELD_FETCHER(MOPS, MOPS, 0b0001);
|
|
|
|
FIELD_FETCHER(HBC, BC, 0b0001);
|
|
|
|
uint64_t PAC_Minor() const {
|
|
return GetField(PAC_frac);
|
|
}
|
|
|
|
FIELD_FETCHER(CLRBHB, CLRBHB, 0b0001);
|
|
|
|
FIELD_FETCHER(SYSREG128, SYSREG_128, 0b0001);
|
|
|
|
FIELD_FETCHER(SYSINSTR128, SYSINSTR_128, 0b0001);
|
|
|
|
FIELD_FETCHER(PRFMSLC, PRFMSLC, 0b0001);
|
|
|
|
FIELD_FETCHER(RPRFM, RPRFM, 0b0001);
|
|
|
|
FIELD_FETCHER(CSSC, CSSC, 0b0001);
|
|
|
|
private:
|
|
enum Field {
|
|
WFxt = 0 * 4,
|
|
RPRES = 1 * 4,
|
|
GPA3 = 2 * 4,
|
|
APA3 = 3 * 4,
|
|
MOPS = 4 * 4,
|
|
BC = 5 * 4,
|
|
PAC_frac = 6 * 4,
|
|
CLRBHB = 7 * 4,
|
|
SYSREG_128 = 8 * 4,
|
|
SYSINSTR_128 = 9 * 4,
|
|
PRFMSLC = 10 * 4,
|
|
RES0 = 11 * 4,
|
|
RPRFM = 12 * 4,
|
|
CSSC = 13 * 4,
|
|
RES1 = 14 * 4,
|
|
ATS1A = 15 * 4,
|
|
};
|
|
};
|
|
|
|
class SVEVLReg final : public FeatureReg {};
|
|
#undef FIELD_FETCHER
|
|
|
|
|
|
ISAR0Reg ISAR0;
|
|
PFR0Reg PFR0;
|
|
PFR1Reg PFR1;
|
|
MIDRReg MIDR;
|
|
ISAR1Reg ISAR1;
|
|
MMFR0Reg MMFR0;
|
|
ZFR0Reg ZFR0;
|
|
MMFR2Reg MMFR2;
|
|
MMFR1Reg MMFR1;
|
|
ISAR2Reg ISAR2;
|
|
DCZIDReg DCZID;
|
|
SVEVLReg SVEVL;
|
|
|
|
static_assert(FEXCore::ToUnderlying(Feature::MAX) < 128);
|
|
static_assert((FEXCore::ToUnderlying(Feature::MAX) / (sizeof(uint64_t) * 8)) == 1);
|
|
|
|
bool Supports(Feature feat) const {
|
|
const size_t DWordSelect = FEXCore::ToUnderlying(feat) / (sizeof(uint64_t) * 8);
|
|
const size_t BitSelect = FEXCore::ToUnderlying(feat) - (DWordSelect * (sizeof(uint64_t) * 8));
|
|
return (FeatureBits[DWordSelect] >> BitSelect) & 1;
|
|
}
|
|
|
|
void RemoveFeature(Feature feat) {
|
|
const size_t DWordSelect = FEXCore::ToUnderlying(feat) / (sizeof(uint64_t) * 8);
|
|
const size_t BitSelect = FEXCore::ToUnderlying(feat) - (DWordSelect * (sizeof(uint64_t) * 8));
|
|
FeatureBits[DWordSelect] &= ~(1ULL << BitSelect);
|
|
}
|
|
|
|
const DCZIDReg& GetDCZID() const {
|
|
return DCZID;
|
|
}
|
|
|
|
uint64_t GetSVEVectorLengthInBits() const {
|
|
return SVEVL.Get();
|
|
}
|
|
|
|
protected:
|
|
void FillFeatureFlags();
|
|
|
|
uint64_t FeatureBits[(FEXCore::ToUnderlying(Feature::MAX) / (sizeof(uint64_t) * 8)) + 1] {};
|
|
|
|
void SetFeature(Feature feat) {
|
|
const size_t DWordSelect = FEXCore::ToUnderlying(feat) / (sizeof(uint64_t) * 8);
|
|
const size_t BitSelect = FEXCore::ToUnderlying(feat) - (DWordSelect * (sizeof(uint64_t) * 8));
|
|
FeatureBits[DWordSelect] |= 1ULL << BitSelect;
|
|
}
|
|
};
|
|
|
|
void FillMIDRInformationViaLinux(FEXCore::HostFeatures* Features);
|
|
|
|
void FetchHostFeatures(FEX::CPUFeatures& Features, FEXCore::HostFeatures& HostFeatures, bool SupportsCacheMaintenanceOps, uint64_t CTR,
|
|
uint64_t MIDR);
|
|
FEXCore::HostFeatures FetchHostFeatures();
|
|
FEX::CPUFeatures GetCPUFeaturesFromIDRegisters();
|
|
} // namespace FEX
|