mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 14:00:16 +02:00
Ryan Houdek
82f936cb6d
NFC Finally converts the IR operations themselves to store the OpSize for the IR operation size and element sizes. This also finally, FINALLY, converts that remaining `_Constant` helper to stop using a size field that is specified in bits rather than bytes like all the other IR op handlers. That thing was so confusing and now it's gone.
833 lines
31 KiB
Python
Executable File
833 lines
31 KiB
Python
Executable File
#!/bin/python3
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import json
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import sys
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from dataclasses import dataclass, field
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import textwrap
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def ExitError(msg):
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print(msg)
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sys.exit(-1)
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@dataclass
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class IRType:
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IRName: str
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CXXName: str
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def __init__(self, IRName, CXXName):
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self.IRName = IRName
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self.CXXName = CXXName
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@dataclass
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class OpArgument:
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Type: str
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IsSSA: bool
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Temporary: bool
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Name: str
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NameWithPrefix: str
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DefaultInitializer: str
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def __init__(self):
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self.Type = None
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self.IsSSA = False
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self.Temporary = False
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self.Name = None
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self.NameWithPrefix = None
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self.DefaultInitializer = None
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return
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def print(self):
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attrs = vars(self)
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print(", ".join("%s: %s" % item for item in attrs.items()))
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@dataclass
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class OpDefinition:
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Name: str
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HasDest: bool
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DestType: str
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DestSize: str
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NumElements: str
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OpClass: str
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HasSideEffects: bool
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ImplicitFlagClobber: bool
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RAOverride: int
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SwitchGen: bool
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ArgPrinter: bool
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SSAArgNum: int
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NonSSAArgNum: int
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DynamicDispatch: bool
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LoweredX87: bool
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JITDispatch: bool
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JITDispatchOverride: str
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TiedSource: int
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Arguments: list
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EmitValidation: list
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Desc: list
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def __init__(self):
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self.Name = None
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self.HasDest = False
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self.DestType = None
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self.DestSize = None
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self.NumElements = None
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self.OpClass = None
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self.OpSize = 0
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self.HasSideEffects = False
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self.ImplicitFlagClobber = False
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self.RAOverride = -1
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self.SwitchGen = True
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self.ArgPrinter = True
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self.SSAArgNum = 0
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self.NonSSAArgNum = 0
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self.DynamicDispatch = False
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self.LoweredX87 = False
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self.JITDispatch = True
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self.JITDispatchOverride = None
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self.TiedSource = -1
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self.Arguments = []
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self.EmitValidation = []
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self.Desc = []
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return
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def print(self):
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attrs = vars(self)
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print(", ".join("%s: %s" % item for item in attrs.items()))
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IRTypesToCXX = {}
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CXXTypeToIR = {}
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IROps = []
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IROpNameMap = {}
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def is_ssa_type(type):
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if (type == "SSA" or
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type == "GPR" or
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type == "GPRPair" or
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type == "FPR"):
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return True
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return False
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def parse_irtypes(irtypes):
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for op_key, op_val in irtypes.items():
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IRTypesToCXX[op_key] = IRType(op_key, op_val)
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CXXTypeToIR[op_val] = IRType(op_key, op_val)
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def parse_ops(ops):
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for op_class, opslist in ops.items():
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for op, op_val in opslist.items():
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if "Ignore" in op_val:
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# Skip these
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continue
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OpDef = OpDefinition()
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# Check if we have a destination
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# Only happens if the IR name contains `=`
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EqualSplit = op.split("=", 1)
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RHS = EqualSplit[0].strip()
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if len(EqualSplit) > 1:
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LHS = EqualSplit[0].strip()
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RHS = EqualSplit[1].strip()
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if ":" in LHS:
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# Named destinations. This is a hack, but so is the entire
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# multi-destination support bolten onto the old IR...
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#
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# Named destinations require side effects because they break
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# SSA hard. Validate that.
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assert("HasSideEffects" in op_val and op_val["HasSideEffects"])
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for Dest in LHS.split(","):
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Dest = Dest.strip()
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DType, Name = Dest.split(":$")
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# If the destination appears also as a source, it is
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# read-modify-write.
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if Dest in RHS:
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# Turn RMW into an in/out source
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RHS = RHS.replace(Dest.strip(), f"{DType}:$Inout{Name}")
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else:
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# Turn named destinations into an out source.
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RHS += f", {DType}:$Out{Name}"
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else:
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# Single anonymous destination
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if LHS not in ["SSA", "GPR", "GPRPair", "FPR"]:
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ExitError(f"Unknown destination class type {LHS}. Needs to be one of SSA, GPR, GPRPair, FPR")
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OpDef.HasDest = True
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OpDef.DestType = LHS
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# IR Op needs to start with a name
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RHS = RHS.split(" ", 1)
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if len(RHS) < 1:
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ExitError("Missing IR op name. Needs to be a string")
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# Set the op name
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OpDef.Name = RHS[0]
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# Parse the arguments
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if len(RHS) > 1:
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Arguments = RHS[1].strip().split(",")
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for Argument in Arguments:
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Argument = Argument.strip()
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OpArg = OpArgument()
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Split = Argument.split(":", 1)
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if len(Split) != 2:
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ExitError("Error parsing argument. Missing Type and name colon split")
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# Type is the first argument
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OpArg.Type = Split[0]
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# Validate typing is in our type map
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if not OpArg.Type in IRTypesToCXX:
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ExitError("IR type {} isn't in IR type map. From IR op {}, argument {}".format(OpArg.Type, OpDef.Name, Argument))
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# Style is the first byte of the name
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if Split[1][0] == "#":
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OpArg.Temporary = True
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OpArg.IsSSA = False
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elif Split[1][0] == "$":
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OpArg.Temporary = False
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OpArg.IsSSA = is_ssa_type(OpArg.Type)
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if OpArg.IsSSA:
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OpDef.SSAArgNum = OpDef.SSAArgNum + 1
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else:
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OpDef.NonSSAArgNum = OpDef.NonSSAArgNum + 1
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else:
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ExitError("IR Op {} missing value argument style specifier. Needs to be one of {{#, $}}".format(OpDef.Name))
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Prefix = Split[1][0]
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ArgName = Split[1][1:]
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NameWithPrefix = Prefix + ArgName
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if len(ArgName) == 0:
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ExitError("Argument is missing variable name")
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DefaultInit = ArgName.split("{", 1)
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if len(DefaultInit) > 1:
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# We have a default initializer, need to do some more work
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# First argument will still be the argument name
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ArgName = DefaultInit[0].strip()
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NameWithPrefix = Prefix + ArgName
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# Second argument will be the default initializer
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# Since we stripped the opening curly brace then it'll end with a closing brace
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if DefaultInit[1][-1] != "}":
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ExitError("IR op {} Argument {} is missing closing curly brace in default initializer?".format(OpDef.Name, ArgName))
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OpArg.DefaultInitializer = DefaultInit[1][:-1]
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# If SSA type then we can generate validation for this op
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if (OpArg.IsSSA and
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(OpArg.Type == "GPR" or
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OpArg.Type == "GPRPair" or
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OpArg.Type == "FPR")):
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OpDef.EmitValidation.append(f"GetOpRegClass({ArgName}) == InvalidClass || WalkFindRegClass({ArgName}) == {OpArg.Type}Class")
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OpArg.Name = ArgName
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OpArg.NameWithPrefix = NameWithPrefix
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OpDef.Arguments.append(OpArg)
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# Additional metadata
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if "DestSize" in op_val:
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OpDef.DestSize = op_val["DestSize"]
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if "NumElements" in op_val:
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OpDef.NumElements = op_val["NumElements"]
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if len(op_class):
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OpDef.OpClass = op_class
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if "HasSideEffects" in op_val:
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OpDef.HasSideEffects = bool(op_val["HasSideEffects"])
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if "ImplicitFlagClobber" in op_val:
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OpDef.ImplicitFlagClobber = bool(op_val["ImplicitFlagClobber"])
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if "ArgPrinter" in op_val:
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OpDef.ArgPrinter = bool(op_val["ArgPrinter"])
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if "RAOverride" in op_val:
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OpDef.RAOverride = int(op_val["RAOverride"])
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if "SwitchGen" in op_val:
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OpDef.SwitchGen = op_val["SwitchGen"]
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if "EmitValidation" in op_val:
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OpDef.EmitValidation.extend(op_val["EmitValidation"])
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if "Desc" in op_val:
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OpDef.Desc = op_val["Desc"]
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if "DynamicDispatch" in op_val:
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OpDef.DynamicDispatch = bool(op_val["DynamicDispatch"])
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if "JITDispatch" in op_val:
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OpDef.JITDispatch = bool(op_val["JITDispatch"])
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if "JITDispatchOverride" in op_val:
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OpDef.JITDispatchOverride = op_val["JITDispatchOverride"]
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if "X87" in op_val:
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OpDef.LoweredX87 = op_val["X87"]
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# X87 implies !JITDispatch
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assert("JITDispatch" not in op_val)
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OpDef.JITDispatch = False
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if "TiedSource" in op_val:
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OpDef.TiedSource = op_val["TiedSource"]
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# Do some fixups of the data here
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if len(OpDef.EmitValidation) != 0:
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for i in range(len(OpDef.EmitValidation)):
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# Patch up all the argument names
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for Arg in OpDef.Arguments:
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# Temporary ops just replace all instances no prefix variant
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OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, Arg.Name)
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#OpDef.print()
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# Error on duplicate op
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if OpDef.Name in IROpNameMap:
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ExitError("Duplicate Op defined! {}".format(OpDef.Name))
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IROps.append(OpDef)
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IROpNameMap[OpDef.Name] = 1
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# Print out enum values
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def print_enums():
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output_file.write("#ifdef IROP_ENUM\n")
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output_file.write("enum IROps : uint16_t {\n")
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for op in IROps:
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output_file.write("\tOP_{},\n" .format(op.Name.upper()))
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output_file.write("};\n")
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output_file.write("#undef IROP_ENUM\n")
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output_file.write("#endif\n\n")
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def print_ir_structs(defines):
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output_file.write("#ifdef IROP_STRUCTS\n")
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# Print out defines here
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for op_val in defines:
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if op_val:
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output_file.write("\t%s;\n" % op_val)
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else:
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output_file.write("\n")
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# Emit the default struct first
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output_file.write("// Default structs\n")
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output_file.write("struct __attribute__((packed)) IROp_Header {\n")
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output_file.write("\tvoid* Data[0];\n")
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output_file.write("\tIROps Op;\n\n")
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output_file.write("\tIR::OpSize Size;\n")
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output_file.write("\tIR::OpSize ElementSize;\n")
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output_file.write("\ttemplate<typename T>\n")
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output_file.write("\tT const* C() const { return reinterpret_cast<T const*>(Data); }\n")
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output_file.write("\ttemplate<typename T>\n")
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output_file.write("\tT* CW() { return reinterpret_cast<T*>(Data); }\n")
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output_file.write("\tOrderedNodeWrapper Args[0];\n")
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output_file.write("};\n\n");
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output_file.write("static_assert(sizeof(IROp_Header) == sizeof(uint32_t), \"IROp_Header should be 32-bits in size\");\n\n");
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# Now the user defined types
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output_file.write("// User defined IR Op structs\n")
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for op in IROps:
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output_file.write("struct __attribute__((packed)) IROp_{} {{\n".format(op.Name))
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output_file.write("\tIROp_Header Header;\n")
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# SSA arguments have a hard requirement to appear after the header
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if op.SSAArgNum > 0:
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output_file.write("\t// SSA arguments\n")
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# Walk the SSA arguments and place them in order of declaration
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for arg in op.Arguments:
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if arg.IsSSA:
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output_file.write("\tOrderedNodeWrapper {};\n".format(arg.Name));
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# Non-SSA arguments are also placed in order of declaration, after SSA though
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if op.NonSSAArgNum > 0:
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output_file.write("\t// Non-SSA arguments\n")
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for arg in op.Arguments:
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if not arg.Temporary and not arg.IsSSA:
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CType = IRTypesToCXX[arg.Type].CXXName
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output_file.write("\t{} {};\n".format(CType, arg.Name));
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output_file.write("\tstatic constexpr IROps OPCODE = OP_{};\n".format(op.Name.upper()))
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if op.SSAArgNum > 0:
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output_file.write("\t// Get index of argument by name\n")
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SSAArg = 0
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for arg in op.Arguments:
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if arg.IsSSA:
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output_file.write("\tstatic constexpr size_t {}_Index = {};\n".format(arg.Name, SSAArg))
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SSAArg = SSAArg + 1
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output_file.write("};\n")
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# Add a static assert that the IR ops must be pod
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output_file.write("static_assert(std::is_trivial_v<IROp_{}>);\n".format(op.Name))
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output_file.write("static_assert(std::is_standard_layout_v<IROp_{}>);\n\n".format(op.Name))
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output_file.write("#undef IROP_STRUCTS\n")
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output_file.write("#endif\n\n")
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# Print out const expression to calculate IR Op sizes
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def print_ir_sizes():
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output_file.write("#ifdef IROP_SIZES\n")
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output_file.write("constexpr std::array<size_t, IROps::OP_LAST + 1> IRSizes = {\n")
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for op in IROps:
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if op.Name == "Last":
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output_file.write("\t-1ULL,\n")
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else:
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output_file.write(f"\tsizeof(IROp_{op.Name}),\n")
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output_file.write(textwrap.dedent("""
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};
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// Make sure our array maps directly to the IROps enum
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static_assert(IRSizes[IROps::OP_LAST] == -1ULL);
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[[maybe_unused, nodiscard]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }
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[[nodiscard, gnu::const, gnu::visibility("default")]] std::string_view const& GetName(IROps Op);
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[[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetArgs(IROps Op);
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[[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetRAArgs(IROps Op);
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[[nodiscard, gnu::const, gnu::visibility("default")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);
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[[nodiscard, gnu::const, gnu::visibility("default")]] bool HasSideEffects(IROps Op);
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[[nodiscard, gnu::const, gnu::visibility("default")]] bool ImplicitFlagClobber(IROps Op);
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[[nodiscard, gnu::const, gnu::visibility("default")]] bool GetHasDest(IROps Op);
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[[nodiscard, gnu::const, gnu::visibility("default")]] bool LoweredX87(IROps Op);
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[[nodiscard, gnu::const, gnu::visibility("default")]] int8_t TiedSource(IROps Op);
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#undef IROP_SIZES
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#endif
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"""))
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def print_ir_reg_classes():
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output_file.write("#ifdef IROP_REG_CLASSES_IMPL\n")
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output_file.write("constexpr std::array<FEXCore::IR::RegisterClassType, IROps::OP_LAST + 1> IRRegClasses = {\n")
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for op in IROps:
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if op.Name == "Last":
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output_file.write("\tFEXCore::IR::InvalidClass,\n")
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else:
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Class = "Invalid"
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if op.HasDest and op.DestType == None:
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ExitError("IR op {} has destination with no destination class".format(op.Name))
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if op.HasDest and op.DestType == "SSA": # Special case SSA type
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output_file.write("\tFEXCore::IR::ComplexClass,\n")
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elif op.HasDest:
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output_file.write("\tFEXCore::IR::{}Class,\n".format(op.DestType))
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else:
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# No destination so it has an invalid destination class
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output_file.write("\tFEXCore::IR::InvalidClass, // No destination\n")
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output_file.write("};\n\n")
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output_file.write("// Make sure our array maps directly to the IROps enum\n")
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output_file.write("static_assert(IRRegClasses[IROps::OP_LAST] == FEXCore::IR::InvalidClass);\n\n")
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output_file.write("FEXCore::IR::RegisterClassType GetRegClass(IROps Op) { return IRRegClasses[Op]; }\n\n")
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output_file.write("#undef IROP_REG_CLASSES_IMPL\n")
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output_file.write("#endif\n\n")
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# Print out the name printer implementation
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def print_ir_getname():
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output_file.write("#ifdef IROP_GETNAME_IMPL\n")
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output_file.write("constexpr std::array<std::string_view const, OP_LAST + 1> IRNames = {\n")
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for op in IROps:
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output_file.write("\t\"{}\",\n".format(op.Name))
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output_file.write("};\n\n")
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output_file.write("static_assert(IRNames[OP_LAST] == \"Last\");\n\n")
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output_file.write("std::string_view const& GetName(IROps Op) {\n")
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output_file.write(" return IRNames[Op];\n")
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output_file.write("}\n")
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output_file.write("#undef IROP_GETNAME_IMPL\n")
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output_file.write("#endif\n\n")
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# Print out the number of SSA args that need to be RA'd
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def print_ir_getraargs():
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output_file.write("#ifdef IROP_GETRAARGS_IMPL\n")
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output_file.write("constexpr std::array<uint8_t, OP_LAST + 1> IRRAArgs = {\n")
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for op in IROps:
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SSAArgs = op.SSAArgNum
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if op.RAOverride != -1:
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if op.RAOverride > op.SSAArgNum:
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ExitError("Op {} has RA override of {} which is more than total SSA values {}. This doesn't work".format(op.Name, op.RAOverride, op.SSAArgNum))
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SSAArgs = op.RAOverride
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output_file.write("\t{},\n".format(SSAArgs))
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output_file.write("};\n\n")
|
|
|
|
|
|
output_file.write("constexpr std::array<uint8_t, OP_LAST + 1> IRArgs = {\n")
|
|
for op in IROps:
|
|
SSAArgs = op.SSAArgNum
|
|
output_file.write("\t{},\n".format(SSAArgs))
|
|
|
|
output_file.write("};\n\n")
|
|
|
|
output_file.write("uint8_t GetRAArgs(IROps Op) {\n")
|
|
output_file.write(" return IRRAArgs[Op];\n")
|
|
output_file.write("}\n")
|
|
|
|
output_file.write("uint8_t GetArgs(IROps Op) {\n")
|
|
output_file.write(" return IRArgs[Op];\n")
|
|
output_file.write("}\n")
|
|
|
|
output_file.write("#undef IROP_GETRAARGS_IMPL\n")
|
|
output_file.write("#endif\n\n")
|
|
|
|
def print_ir_hassideeffects():
|
|
output_file.write("#ifdef IROP_HASSIDEEFFECTS_IMPL\n")
|
|
|
|
for prop, T in [
|
|
("HasSideEffects", "bool"),
|
|
("ImplicitFlagClobber", "bool"),
|
|
("LoweredX87", "bool"),
|
|
("TiedSource", "int8_t"),
|
|
]:
|
|
output_file.write(
|
|
f"constexpr std::array<{'uint8_t' if T == 'bool' else T}, OP_LAST + 1> {prop}_ = {{\n"
|
|
)
|
|
for op in IROps:
|
|
if T == "bool":
|
|
output_file.write(
|
|
"\t{},\n".format(("true" if getattr(op, prop) else "false"))
|
|
)
|
|
else:
|
|
output_file.write(f"\t{getattr(op, prop)},\n")
|
|
|
|
output_file.write("};\n\n")
|
|
|
|
output_file.write(f"{T} {prop}(IROps Op) {{\n")
|
|
output_file.write(f" return {prop}_[Op];\n")
|
|
output_file.write("}\n")
|
|
|
|
output_file.write("#undef IROP_HASSIDEEFFECTS_IMPL\n")
|
|
output_file.write("#endif\n\n")
|
|
|
|
def print_ir_gethasdest():
|
|
output_file.write("#ifdef IROP_GETHASDEST_IMPL\n")
|
|
|
|
output_file.write("constexpr std::array<bool, OP_LAST + 1> IRDest = {\n")
|
|
for op in IROps:
|
|
if op.HasDest:
|
|
output_file.write("\ttrue,\n")
|
|
else:
|
|
output_file.write("\tfalse,\n")
|
|
|
|
output_file.write("};\n\n")
|
|
|
|
output_file.write("bool GetHasDest(IROps Op) {\n")
|
|
output_file.write(" return IRDest[Op];\n")
|
|
output_file.write("}\n")
|
|
|
|
output_file.write("#undef IROP_GETHASDEST_IMPL\n")
|
|
output_file.write("#endif\n\n")
|
|
|
|
# Print out IR argument printing
|
|
def print_ir_arg_printer():
|
|
output_file.write("#ifdef IROP_ARGPRINTER_HELPER\n")
|
|
output_file.write("switch (IROp->Op) {\n")
|
|
for op in IROps:
|
|
if not op.ArgPrinter:
|
|
continue
|
|
|
|
output_file.write("case IROps::OP_{}: {{\n".format(op.Name.upper()))
|
|
|
|
if len(op.Arguments) != 0:
|
|
output_file.write("\t[[maybe_unused]] auto Op = IROp->C<IR::IROp_{}>();\n".format(op.Name))
|
|
output_file.write("\t*out << \" \";\n")
|
|
|
|
SSAArgNum = 0
|
|
FirstArg = True
|
|
for i in range(0, len(op.Arguments)):
|
|
arg = op.Arguments[i]
|
|
|
|
# No point printing temporaries that we can't recover
|
|
if arg.Temporary:
|
|
continue
|
|
|
|
if FirstArg:
|
|
FirstArg = False
|
|
else:
|
|
output_file.write('\t*out << ", ";\n')
|
|
|
|
if arg.IsSSA:
|
|
# SSA value
|
|
output_file.write("\tPrintArg(out, IR, Op->Header.Args[{}], RAData);\n".format(SSAArgNum))
|
|
SSAArgNum = SSAArgNum + 1
|
|
else:
|
|
# User defined op that is stored
|
|
output_file.write("\tPrintArg(out, IR, Op->{});\n".format(arg.Name))
|
|
|
|
output_file.write("break;\n")
|
|
output_file.write("}\n")
|
|
|
|
output_file.write("#undef IROP_ARGPRINTER_HELPER\n")
|
|
output_file.write("#endif\n")
|
|
|
|
# Print out IR allocator helpers
|
|
def print_ir_allocator_helpers():
|
|
output_file.write("#ifdef IROP_ALLOCATE_HELPERS\n")
|
|
|
|
output_file.write("\ttemplate <class T>\n")
|
|
output_file.write("\tstruct Wrapper final {\n")
|
|
output_file.write("\t\tT *first;\n")
|
|
output_file.write("\t\tOrderedNode *Node; ///< Actual offset of this IR in ths list\n")
|
|
output_file.write("\n")
|
|
output_file.write("\t\toperator Wrapper<IROp_Header>() const { return Wrapper<IROp_Header> {reinterpret_cast<IROp_Header*>(first), Node}; }\n")
|
|
output_file.write("\t\toperator OrderedNode *() { return Node; }\n")
|
|
output_file.write("\t\toperator const OrderedNode *() const { return Node; }\n")
|
|
output_file.write("\t\toperator OpNodeWrapper () const { return Node->Header.Value; }\n")
|
|
output_file.write("\t};\n")
|
|
|
|
output_file.write("\ttemplate <class T>\n")
|
|
output_file.write("\tusing IRPair = Wrapper<T>;\n\n")
|
|
|
|
output_file.write("\tIRPair<IROp_Header> AllocateRawOp(size_t HeaderSize) {\n")
|
|
output_file.write("\t\tauto Op = reinterpret_cast<IROp_Header*>(DualListData.DataAllocate(HeaderSize));\n")
|
|
output_file.write("\t\tmemset(Op, 0, HeaderSize);\n")
|
|
output_file.write("\t\tOp->Op = IROps::OP_DUMMY;\n")
|
|
output_file.write("\t\treturn IRPair<IROp_Header>{Op, CreateNode(Op)};\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("\ttemplate<class T, IROps T2>\n")
|
|
output_file.write("\tT *AllocateOrphanOp() {\n")
|
|
output_file.write("\t\tsize_t Size = FEXCore::IR::GetSize(T2);\n")
|
|
output_file.write("\t\tauto Op = reinterpret_cast<T*>(DualListData.DataAllocate(Size));\n")
|
|
output_file.write("\t\tmemset(Op, 0, Size);\n")
|
|
output_file.write("\t\tOp->Header.Op = T2;\n")
|
|
output_file.write("\t\treturn Op;\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("\ttemplate<class T, IROps T2>\n")
|
|
output_file.write("\tIRPair<T> AllocateOp() {\n")
|
|
output_file.write("\t\tsize_t Size = FEXCore::IR::GetSize(T2);\n")
|
|
output_file.write("\t\tauto Op = reinterpret_cast<T*>(DualListData.DataAllocate(Size));\n")
|
|
output_file.write("\t\tmemset(Op, 0, Size);\n")
|
|
output_file.write("\t\tOp->Header.Op = T2;\n")
|
|
output_file.write("\t\treturn IRPair<T>{Op, CreateNode(&Op->Header)};\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("\tIR::OpSize GetOpSize(const OrderedNode *Op) const {\n")
|
|
output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
|
|
output_file.write("\t\treturn IR::SizeToOpSize(HeaderOp->Size);\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("\tIR::OpSize GetOpElementSize(const OrderedNode *Op) const {\n")
|
|
output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
|
|
output_file.write("\t\treturn IR::SizeToOpSize(HeaderOp->ElementSize);\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("\tuint8_t GetOpElements(const OrderedNode *Op) const {\n")
|
|
output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
|
|
output_file.write("\t\tLOGMAN_THROW_A_FMT(OpHasDest(Op), \"Op {} has no dest\\n\", GetName(HeaderOp->Op));\n")
|
|
output_file.write("\t\treturn IR::OpSizeToSize(GetOpSize(Op)) / IR::OpSizeToSize(GetOpElementSize(Op));\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("\tbool OpHasDest(const OrderedNode *Op) const {\n")
|
|
output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
|
|
output_file.write("\t\treturn GetHasDest(HeaderOp->Op);\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("\tIROps GetOpType(const OrderedNode *Op) const {\n")
|
|
output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
|
|
output_file.write("\t\treturn HeaderOp->Op;\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("\tFEXCore::IR::RegisterClassType GetOpRegClass(const OrderedNode *Op) const {\n")
|
|
output_file.write("\t\treturn GetRegClass(GetOpType(Op));\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("\tstd::string_view const& GetOpName(const OrderedNode *Op) const {\n")
|
|
output_file.write("\t\treturn IR::GetName(GetOpType(Op));\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
# Generate helpers with operands
|
|
for op in IROps:
|
|
if op.Name != "Last":
|
|
output_file.write("\tIRPair<IROp_{}> _{}(" .format(op.Name, op.Name))
|
|
|
|
# Output SSA args first
|
|
for i in range(0, len(op.Arguments)):
|
|
arg = op.Arguments[i]
|
|
LastArg = len(op.Arguments) - i - 1 == 0
|
|
|
|
if arg.Temporary:
|
|
CType = IRTypesToCXX[arg.Type].CXXName
|
|
output_file.write("{} {}".format(CType, arg.Name));
|
|
elif arg.IsSSA:
|
|
# SSA value
|
|
output_file.write("OrderedNode *{}".format(arg.Name))
|
|
else:
|
|
# User defined op that is stored
|
|
CType = IRTypesToCXX[arg.Type].CXXName
|
|
output_file.write("{} {}".format(CType, arg.Name));
|
|
|
|
if arg.DefaultInitializer != None:
|
|
output_file.write(" = {}".format(arg.DefaultInitializer))
|
|
|
|
if not LastArg:
|
|
output_file.write(", ")
|
|
|
|
output_file.write(") {\n")
|
|
|
|
# Save NZCV if needed before clobbering NZCV
|
|
if op.ImplicitFlagClobber:
|
|
output_file.write("\t\tSaveNZCV(IROps::OP_{});".format(op.Name.upper()))
|
|
|
|
# We gather the "has x87?" flag as we go. This saves the user from
|
|
# having to keep track of whether they emitted any x87.
|
|
# Also changes the mmx state to X87.
|
|
if op.LoweredX87:
|
|
output_file.write("\t\tRecordX87Use();\n")
|
|
output_file.write(
|
|
"\t\tif(MMXState == MMXState_MMX) ChgStateMMX_X87();\n"
|
|
)
|
|
|
|
output_file.write("\t\tauto _Op = AllocateOp<IROp_{}, IROps::OP_{}>();\n".format(op.Name, op.Name.upper()))
|
|
|
|
if op.SSAArgNum != 0:
|
|
output_file.write("\t\tauto ListDataBegin = DualListData.ListBegin();\n")
|
|
for arg in op.Arguments:
|
|
if arg.IsSSA:
|
|
output_file.write("\t\t_Op.first->{} = {}->Wrapped(ListDataBegin);\n".format(arg.Name, arg.Name))
|
|
|
|
if op.SSAArgNum != 0:
|
|
for arg in op.Arguments:
|
|
if arg.IsSSA:
|
|
output_file.write("\t\t{}->AddUse();\n".format(arg.Name))
|
|
|
|
if len(op.Arguments) != 0:
|
|
for arg in op.Arguments:
|
|
if not arg.Temporary and not arg.IsSSA:
|
|
output_file.write("\t\t_Op.first->{} = {};\n".format(arg.Name, arg.Name))
|
|
|
|
if (op.HasDest):
|
|
# We can only infer a size if we have arguments
|
|
if op.DestSize == None:
|
|
# We need to infer destination size
|
|
output_file.write("\t\tIR::OpSize InferSize = OpSize::iUnsized;\n")
|
|
if len(op.Arguments) != 0:
|
|
for arg in op.Arguments:
|
|
if arg.IsSSA:
|
|
output_file.write("\t\tauto Size{} = GetOpSize({});\n".format(arg.Name, arg.Name))
|
|
for arg in op.Arguments:
|
|
if arg.IsSSA:
|
|
output_file.write("\t\tInferSize = std::max(InferSize, Size{});\n".format(arg.Name))
|
|
|
|
output_file.write("\t\t_Op.first->Header.Size = InferSize;\n")
|
|
|
|
# Some ops without a destination still need an operating size
|
|
# Effectively reusing the destination size value for operation size
|
|
if op.DestSize != None:
|
|
output_file.write("\t\t_Op.first->Header.Size = {};\n".format(op.DestSize))
|
|
|
|
if op.NumElements == None:
|
|
output_file.write("\t\t_Op.first->Header.ElementSize = _Op.first->Header.Size;\n")
|
|
else:
|
|
output_file.write("\t\t_Op.first->Header.ElementSize = _Op.first->Header.Size / ({});\n".format(op.NumElements))
|
|
|
|
# Insert validation here
|
|
if op.EmitValidation != None:
|
|
output_file.write("\t\t#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED\n")
|
|
|
|
for Validation in op.EmitValidation:
|
|
Sanitized = Validation.replace("\"", "\\\"")
|
|
output_file.write("\tLOGMAN_THROW_A_FMT({}, \"{}\");\n".format(Validation, Sanitized))
|
|
output_file.write("\t\t#endif\n")
|
|
|
|
output_file.write("\t\treturn _Op;\n")
|
|
output_file.write("\t}\n\n")
|
|
|
|
output_file.write("#undef IROP_ALLOCATE_HELPERS\n")
|
|
output_file.write("#endif\n")
|
|
|
|
def print_ir_dispatcher_defs():
|
|
output_dispatch_file.write("#ifdef IROP_DISPATCH_DEFS\n")
|
|
for op in IROps:
|
|
if op.Name != "Last" and op.SwitchGen and op.JITDispatch and op.JITDispatchOverride == None:
|
|
output_dispatch_file.write("DEF_OP({});\n".format(op.Name))
|
|
|
|
output_dispatch_file.write("#undef IROP_DISPATCH_DEFS\n")
|
|
output_dispatch_file.write("#endif\n")
|
|
|
|
def print_ir_dispatcher_dispatch():
|
|
output_dispatch_file.write("#ifdef IROP_DISPATCH_DISPATCH\n")
|
|
for op in IROps:
|
|
if op.Name != "Last" and op.JITDispatch:
|
|
DispatchName = op.Name
|
|
if op.JITDispatchOverride != None:
|
|
DispatchName = op.JITDispatchOverride
|
|
|
|
if (op.DynamicDispatch):
|
|
output_dispatch_file.write("REGISTER_OP_RT({}, {});\n".format(op.Name.upper(), DispatchName))
|
|
else:
|
|
output_dispatch_file.write("REGISTER_OP({}, {});\n".format(op.Name.upper(), DispatchName))
|
|
|
|
output_dispatch_file.write("#undef IROP_DISPATCH_DISPATCH\n")
|
|
output_dispatch_file.write("#endif\n")
|
|
|
|
|
|
if (len(sys.argv) < 4):
|
|
ExitError()
|
|
|
|
output_filename = sys.argv[2]
|
|
output_dispatcher_filename = sys.argv[3]
|
|
|
|
json_file = open(sys.argv[1], "r")
|
|
json_text = json_file.read()
|
|
json_file.close()
|
|
|
|
json_object = json.loads(json_text)
|
|
json_object = {k.upper(): v for k, v in json_object.items()}
|
|
|
|
ops = json_object["OPS"]
|
|
irtypes = json_object["IRTYPES"]
|
|
defines = json_object["DEFINES"]
|
|
|
|
parse_irtypes(irtypes)
|
|
parse_ops(ops)
|
|
|
|
output_file = open(output_filename, "w")
|
|
|
|
print_enums()
|
|
print_ir_structs(defines)
|
|
print_ir_sizes()
|
|
print_ir_reg_classes()
|
|
print_ir_getname()
|
|
print_ir_getraargs()
|
|
print_ir_hassideeffects()
|
|
print_ir_gethasdest()
|
|
print_ir_arg_printer()
|
|
print_ir_allocator_helpers()
|
|
|
|
output_file.close()
|
|
|
|
output_dispatch_file = open(output_dispatcher_filename, "w")
|
|
print_ir_dispatcher_defs()
|
|
print_ir_dispatcher_dispatch()
|
|
|
|
output_dispatch_file.close()
|