Alyssa Rosenzweig 059d980c33 IR: give StoreRegister a precoloured destination ...

this will eliminate an annoying special case in post-RA opts.

No difference proven at 95.0% confidence

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2025-06-19 13:44:23 -04:00

..

ALUOps.cpp

JIT: drop UDiv extensions

2025-06-12 16:45:49 -04:00

Arm64Relocations.cpp

Drop use of assume-asserting logging macros

2025-01-21 12:01:33 +01:00

AtomicOps.cpp

JIT: make almost all the DEF_OPs common

2025-05-19 13:42:59 -04:00

BranchOps.cpp

JIT: make almost all the DEF_OPs common

2025-05-19 13:42:59 -04:00

ConversionOps.cpp

JIT: make almost all the DEF_OPs common

2025-05-19 13:42:59 -04:00

EncryptionOps.cpp

JIT: make almost all the DEF_OPs common

2025-05-19 13:42:59 -04:00

JIT.cpp

IR: merge ldiv/lrem handlers

2025-06-12 16:45:49 -04:00

JITClass.h

JIT: Re-enable parallel compilation by compiling to a temporary buffer

2025-06-01 22:45:50 +02:00

MemoryOps.cpp

IR: give StoreRegister a precoloured destination

2025-06-19 13:44:23 -04:00

MiscOps.cpp

RegisterAllocationPass: delete trivial instructions

2025-05-26 15:52:23 -04:00

MoveOps.cpp

RegisterAllocationPass: delete trivial instructions

2025-05-26 15:52:23 -04:00

VectorOps.cpp

JIT: make almost all the DEF_OPs common

2025-05-19 13:42:59 -04:00