Ryan Houdek 79ab76b42e AVX128: Optimize vpalignr ...

When the shift size is exactly 16bytes, then it turns in to a move.

If the shift size is above 16-bytes then synthesize the zero register in
the OpcodeDispatcher, so the backend doesn't synthesize and not cache.

2025-03-06 17:10:22 -08:00

..

Config

FEXCore: Implements baseline per-thread profile stats

2025-02-11 12:56:10 -08:00

Context

Core: Remove unused ThreadAddBlockLink interface

2025-02-16 16:30:05 +01:00

Core

AVX128: Optimize vpalignr

2025-03-06 17:10:22 -08:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

IR

IR: Remove some static analysis warnings

2025-03-05 12:30:27 -08:00