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FEX-Emu--FEX/unittests/InstructionCountCI/DDD.json
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Ryan Houdek 200f59ab70 InstcountCI: Update
2026-09-10 09:53:54 -07:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"FRINTTS"
],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"AFP",
"RPRES"
],
"BinaryCacheVersion": 20
},
"Comment": [
"These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",
"This accounts for the overhead of loading and storing the registers in each instruction",
"Could technically save some instructions by using SRA for MMX registers."
],
"Instructions": {
"pi2fw mm0, mm1": {
"ExpectedInstructionCount": 9,
"Comment": [
"0x0f 0x0f 0x0c"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"uzp1 v2.4h, v2.4h, v2.4h",
"sxtl v2.4s, v2.4h",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pi2fd mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": [
"0x0f 0x0f 0x0d"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pf2iw mm0, mm1": {
"ExpectedInstructionCount": 9,
"Comment": [
"0x0f 0x0f 0x1c"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fcvtzs v2.2s, v2.2s",
"sqxtn v2.4h, v2.4s",
"sxtl v2.4s, v2.4h",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pf2id mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": [
"0x0f 0x0f 0x1d"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpv mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": [
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fmov v0.4s, #0x70 (1.0000)",
"fdiv v2.4s, v0.4s, v2.4s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrsqrtv mm0, mm1": {
"ExpectedInstructionCount": 12,
"Comment": [
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fabs v3.4s, v2.4s",
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v3.4s",
"fdiv v3.4s, v0.4s, v1.4s",
"movi v0.2s, #0x80, lsl #24",
"bit v3.8b, v2.8b, v0.8b",
"str d3, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfnacc mm0, mm1": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0x0f 0x8a",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"fsub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfpnacc mm0, mm1": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0x0f 0x8e",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"dup v4.2s, v2.s[1]",
"fsub s2, s2, s4",
"faddp v3.2s, v3.2s, v3.2s",
"mov v2.s[1], v3.s[0]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfcmpge mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0x90",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmge v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfmin mm0, mm1": {
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0x0f 0x94",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmgt v0.4s, v2.4s, v3.4s",
"bif v3.16b, v2.16b, v0.16b",
"str d3, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcp mm0, mm1": {
"ExpectedInstructionCount": 9,
"Comment": [
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fmov s0, #0x70 (1.0000)",
"fdiv s2, s0, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrsqrt mm0, mm1": {
"ExpectedInstructionCount": 13,
"Comment": [
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fabs v3.4s, v2.4s",
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v3.4s",
"fdiv v3.4s, v0.4s, v1.4s",
"movi v0.2s, #0x80, lsl #24",
"bit v3.8b, v2.8b, v0.8b",
"dup v2.2s, v3.s[0]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfsub mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0x9a",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fsub v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfadd mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0x9e",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fadd v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfcmpgt mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xa0",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmgt v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfmax mm0, mm1": {
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0x0f 0xa4",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmgt v0.4s, v3.4s, v2.4s",
"bif v3.16b, v2.16b, v0.16b",
"str d3, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpit1 mm0, mm1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpit1 mm0, mm0": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrsqit1 mm0, mm1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrsqit1 mm0, mm0": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfsubr mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xaa",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fsub v2.4s, v2.4s, v3.4s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfcmpeq mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xb0",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmeq v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfmul mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xb4",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fmul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpit2 mm0, mm1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpit2 mm0, mm0": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"db 0x0f, 0x0f, 0xc1, 0xb7": {
"ExpectedInstructionCount": 11,
"Comment": [
"nasm doesn't support emitting this instruction",
"pmulhrw mm0, mm1",
"0x0f 0x0f 0xb7"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"smull v2.4s, v2.4h, v3.4h",
"movi v3.4s, #0x80, lsl #8",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #16",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pswapd mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x0f 0xbb",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"rev64 v2.2s, v2.2s",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pavgusb mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xbf",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"urhadd v2.16b, v3.16b, v2.16b",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
}
}
}
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