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https://github.com/FEX-Emu/FEX.git
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Alyssa Rosenzweig
725d0e187a
I recommend viewing the new source file as the diff is quite messy. --- The old RA commits every "how not to write an RA" sin in the book. Chaitin spill-one loop? Check. Potential spilling caused by alignment issues since there's no live range splitting? Check. Panic spilling? Check. Generating an interference graph with linear live ranges, so you get the code quality of linear scan with the cost of graph colouring? Check. ... It is wholly unsuitable to any application, and specifically unsuitable for FEX. --- The new RA exploits a key IR invariant unique to FEX: no values are live across block boundaries. This is validated. Because of this invariant, all RA is block local. This lets us use a dead simple 2 pass RA that generates ~optimal code in linear time. The first pass walks the IR backwards, analyzing the IR. This is a souped up analogue to liveness analysis. The second pass walks the IR forward, blasting out registers. If necessary, it will insert spill and/or shuffle code on the fly. Spilling uses the well-known furthest-first heuristic, which has excellent results for straight line code. That's it :-) Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
124 lines
3.8 KiB
C++
124 lines
3.8 KiB
C++
// SPDX-License-Identifier: MIT
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/*
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$info$
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meta: ir|opts ~ IR to IR Optimization
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tags: ir|opts
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desc: Defines which passes are run, and runs them
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$end_info$
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*/
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#include "Interface/Context/Context.h"
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#include "Interface/IR/PassManager.h"
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#include "Interface/IR/Passes.h"
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#include "Interface/IR/Passes/RegisterAllocationPass.h"
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/Utils/Profiler.h>
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namespace FEXCore::IR {
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class IREmitter;
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void PassManager::Finalize() {
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if (!PassManagerDumpIR()) {
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// Not configured to dump any IR, just return.
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return;
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}
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auto it = Passes.begin();
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// Walk the passes and add them where asked.
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if (PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::BEFOREOPT) {
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// Insert at the start.
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it = InsertAt(it, Debug::CreateIRDumper());
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++it; // Skip what we inserted.
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}
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if ((PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::BEFOREPASS) ||
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(PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::AFTERPASS)) {
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bool SkipFirstBefore = PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::BEFOREOPT;
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for (; it != Passes.end();) {
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if (PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::BEFOREPASS) {
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if (SkipFirstBefore) {
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// If we need to skip the first one, then continue.
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SkipFirstBefore = false;
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++it;
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continue;
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}
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// Insert before
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it = InsertAt(it, Debug::CreateIRDumper());
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++it; // Skip what we inserted.
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}
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++it; // Skip current pass.
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if (PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::AFTERPASS) {
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// Insert after
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it = InsertAt(it, Debug::CreateIRDumper());
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++it; // Skip what we inserted.
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}
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}
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}
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if (PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::AFTEROPT) {
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if (!(PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::AFTERPASS)) {
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// Insert final IRDumper.
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InsertAt(Passes.end(), Debug::CreateIRDumper());
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}
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}
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}
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void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl* ctx, bool InlineConstants) {
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FEX_CONFIG_OPT(DisablePasses, O0);
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if (!DisablePasses()) {
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InsertPass(CreateContextLoadStoreElimination(ctx->HostFeatures.SupportsAVX));
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if (Is64BitMode()) {
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// This needs to run after RCLSE
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// This only matters for 64-bit code since these instructions don't exist in 32-bit
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InsertPass(CreateLongDivideEliminationPass());
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}
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InsertPass(CreateDeadStoreElimination());
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InsertPass(CreatePassDeadCodeElimination());
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InsertPass(CreateConstProp(InlineConstants, ctx->HostFeatures.SupportsTSOImm9, Is64BitMode()));
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InsertPass(CreateDeadFlagCalculationEliminination());
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InsertPass(CreateInlineCallOptimization(&ctx->CPUID));
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InsertPass(CreatePassDeadCodeElimination());
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}
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// If the IR is compacted post-RA then the node indexing gets messed up and the backend isn't able to find the register assigned to a node
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// Compact before IR, don't worry about RA generating spills/fills
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InsertPass(CreateIRCompaction(ctx->OpDispatcherAllocator), "Compaction");
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}
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void PassManager::AddDefaultValidationPasses() {
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#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
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InsertValidationPass(Validation::CreateIRValidation(), "IRValidation");
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InsertValidationPass(Validation::CreateRAValidation());
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#endif
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}
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void PassManager::InsertRegisterAllocationPass() {
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InsertPass(IR::CreateRegisterAllocationPass(), "RA");
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}
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bool PassManager::Run(IREmitter* IREmit) {
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FEXCORE_PROFILE_SCOPED("PassManager::Run");
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bool Changed = false;
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for (const auto& Pass : Passes) {
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Changed |= Pass->Run(IREmit);
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}
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#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
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for (const auto& Pass : ValidationPasses) {
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Changed |= Pass->Run(IREmit);
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}
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#endif
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return Changed;
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}
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} // namespace FEXCore::IR
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