mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-13 01:00:46 +02:00
Billy Laws
4877bb3f19
This is required for handling SMC with the ResetToConsistentState arguments as used in Windows, as using the NTDLL exported NtContinue would wipe out any reserved registers in the ARM64EC ABI. For Windows the syscall numbers are somewhat stable, and the SVC instruction can be called directly. Since wine doesn't handle that on ARM64, hardcode the system call number and manually call into wine dispatcher. Once wine gains proper syscall thunks, those can be parsed to get the number and the hardcoding dropped.
101 lines
3.4 KiB
ArmAsm
101 lines
3.4 KiB
ArmAsm
.text
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.balign 16
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// __os_arm64x_x64_jump in ARM64EC docs
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// Expects target code address in x9
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.globl DispatchJump
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DispatchJump:
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str lr, [sp, #-8]! // Push return address to stack, this will be popped by the x86 RET instr.
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b check_target_ec
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// __os_arm64x_dispatch_ret in ARM64EC docs
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// Expects target code address in lr
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.globl RetToEntryThunk
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RetToEntryThunk:
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mov x9, lr
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check_target_ec:
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// Check if target is in fact x86 code
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ldr x16, [x18, #0x60] // TEB->PEB
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ldr x16, [x16, #0x368] // PEB->EcCodeBitMap
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lsr x17, x9, #15
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and x17, x17, #0x1fffffffffff8
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ldr x16, [x16, x17]
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lsr x17, x9, #12
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lsr x16, x16, x17
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tbnz x16, #0, ExitFunctionEC
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b enter_jit
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// __os_arm64x_dispatch_call_no_redirect in ARM64EC docs
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// Expects target code address in x9, and to be called using a 'blr x16' instruction.
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.globl ExitToX64
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ExitToX64:
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str lr, [sp, #-8]! // Push return address to stack, this will be popped by the x86 RET instr.
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enter_jit:
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ldr x17, [x18, #0x1788] // TEB->ChpeV2CpuAreaInfo
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ldr x16, [x17, #0x40] // ChpeV2CpuAreaInfo->EmulatorData[2] - DispatcherLoopTopEnterEC
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br x16 // DispatcherLoopTopEnterEC(RIP:x9, CPUArea:x17)
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// Invoked by KiUserEmulationDispatcher after e.g. an NtContinue to x86 code
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// Expects a CONTEXT pointer in x0
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.global BeginSimulation
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BeginSimulation:
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ldr x17, [x18, #0x1788] // TEB->ChpeV2CpuAreaInfo
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ldr x16, [x17, #0x8] // ChpeV2CpuAreaInfo->EmulatorStackBase
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mov sp, x16
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bl "#SyncThreadContext"
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ldr x17, [x18, #0x1788] // TEB->ChpeV2CpuAreaInfo
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ldr x16, [x17, #0x48] // ChpeV2CpuAreaInfo->EmulatorData[3] - DispatcherLoopTopEnterECFillSRA
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br x16 // DispatcherLoopTopEnterECFillSRA(CPUArea:x17)
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// Called into by FEXCore
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// Expects the target code address in x9
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.global ExitFunctionEC
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ExitFunctionEC:
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// Either return to an exit thunk (return to ARM64EC function) or call an entry thunk (call to ARM64EC function).
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// It is assumed that a 'blr x16' instruction is only ever used to call into x86 code from an exit thunk, and that all
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// exported ARM64EC functions have a 4-byte offset to their entry thunk immediately before their first instruction.
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mov x17, x9
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mov w16, #0x200
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movk w16, #0xd63f, lsl 16 // blr x16
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ldursw x23, [x17, #-0x4] // Load either the entry thunk offset or the calling instruction.
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cmp w23, w16
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beq ret_sp_aligned
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and x23, x23, #-0x4
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add x17, x17, x23 // Resolve entry thunk address.
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mov x4, sp
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tbz x4, #3, ret_sp_misaligned
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ldr lr, [x4], #0x8 // Pop the return address into lr.
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mov sp, x4
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ret_sp_aligned:
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br x17
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ret_sp_misaligned:
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// In the case of the x64 caller leaving sp only 8-byte aligned, leave the return address on the stack to keep 16-byte
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// alignment and have the callee return to an x86 ret instruction. FEX can then return to the actual caller keeping
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// the misaligned RSP.
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adrp lr, X64ReturnInstr
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ldr lr, [lr, #:lo12:X64ReturnInstr]
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br x17
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// Calls NtContinue directly to allow continuing from a full native context, as the NTDLL NtContinue export takes in
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// an x64 context with EC and the conversion to that loses the ARM64EC ABI-disallowed registers that FEX uses.
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.global "#NtContinueNative"
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"#NtContinueNative":
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adrp x16, WineSyscallDispatcher
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ldr x16, [x16, #:lo12:WineSyscallDispatcher]
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cbz x16, direct_syscall
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wine_syscall:
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mov x9, x30
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adrp x8, WineNtContinueSyscallId
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ldr x8, [x8, #:lo12:WineNtContinueSyscallId]
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blr x16
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ret
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direct_syscall:
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svc #0x43
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ret
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