mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 13:00:15 +02:00
6508 lines
169 KiB
JSON
6508 lines
169 KiB
JSON
{
|
|
"Features": {
|
|
"Bitness": 64,
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|
"EnabledHostFeatures": [
|
|
"SVE128",
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|
"SVE256"
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|
],
|
|
"DisabledHostFeatures": [
|
|
"FCMA"
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|
]
|
|
},
|
|
"Instructions": {
|
|
"vmovups xmm0, xmm0": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Spurious moves",
|
|
"Map 1 0b00 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovups xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"SVE 128-bit load already zero's the upper bits",
|
|
"Spurious move afterwards",
|
|
"Map 1 0b00 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovups ymm0, ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Spurious moves",
|
|
"Map 1 0b00 0x10 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovups ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Doesn't load directly in to destination",
|
|
"Map 1 0b00 0x10 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovupd xmm0, xmm0": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Spurious moves",
|
|
"Map 1 0b01 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovupd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"SVE 128-bit load already zero's the upper bits",
|
|
"Spurious move afterwards",
|
|
"Map 1 0b01 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovupd ymm0, ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Spurious moves",
|
|
"Map 1 0b01 0x10 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovupd ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Doesn't load directly in to destination",
|
|
"Map 1 0b01 0x10 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovss xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"32-bit vector load already zero's the upper bits",
|
|
"Spurious move afterwards",
|
|
"Map 1 0b10 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b10 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovsd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"32-bit vector load already zero's the upper bits",
|
|
"Spurious move afterwards",
|
|
"Map 1 0b11 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b11 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
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|
]
|
|
},
|
|
"vmovups [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str q2, [x4]"
|
|
]
|
|
},
|
|
"vmovups [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x11 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"st1b {z2.b}, p7, [x4]"
|
|
]
|
|
},
|
|
"vmovupd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str q2, [x4]"
|
|
]
|
|
},
|
|
"vmovupd [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x11 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"st1b {z2.b}, p7, [x4]"
|
|
]
|
|
},
|
|
"vmovss [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str s2, [x4]"
|
|
]
|
|
},
|
|
"db 0xc5, 0xf2, 0x11, 0xc2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"vmovss xmm2, xmm1, xmm0",
|
|
"Need to manually encode since nasm won't encode this",
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b10 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z16.d",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z18.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovsd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str d2, [x4]"
|
|
]
|
|
},
|
|
"db 0xc5, 0xf3, 0x11, 0xc2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"vmovsd xmm2, xmm1, xmm0",
|
|
"Need to manually encode since nasm won't encode this",
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b11 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z16.d",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z18.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovlps xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b00 0x12 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ldr q3, [x4]",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovlpd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b01 0x12 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ldr q3, [x4]",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovsldup xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x12 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"trn1 v2.4s, v2.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovsldup ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x12 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"trn1 z2.s, z2.s, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovddup xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x12 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"dup v2.2d, v2.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovddup ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x12 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"trn1 z2.d, z2.d, z2.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovlps [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x13 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str d2, [x4]"
|
|
]
|
|
},
|
|
"vmovlpd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x13 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str d2, [x4]"
|
|
]
|
|
},
|
|
"vunpcklps xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x14 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ldr q3, [x4]",
|
|
"zip1 v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vunpcklps ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x14 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ld1b {z3.b}, p7/z, [x4]",
|
|
"zip1 z4.s, z2.s, z3.s",
|
|
"zip2 z2.s, z2.s, z3.s",
|
|
"mov z1.q, q2",
|
|
"mov z2.d, z4.d",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z2.b, p0/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vunpcklpd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x14 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ldr q3, [x4]",
|
|
"zip1 v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vunpcklpd ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x14 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ld1b {z3.b}, p7/z, [x4]",
|
|
"zip1 z4.d, z2.d, z3.d",
|
|
"zip2 z2.d, z2.d, z3.d",
|
|
"mov z1.q, q2",
|
|
"mov z2.d, z4.d",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z2.b, p0/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vunpckhps xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x15 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ldr q3, [x4]",
|
|
"zip2 v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vunpckhps ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x15 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ld1b {z3.b}, p7/z, [x4]",
|
|
"zip1 z4.s, z2.s, z3.s",
|
|
"zip2 z2.s, z2.s, z3.s",
|
|
"mov z1.q, z4.q[1]",
|
|
"mov z2.b, p6/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vunpckhpd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x15 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ldr q3, [x4]",
|
|
"zip2 v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vunpckhpd ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x15 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ld1b {z3.b}, p7/z, [x4]",
|
|
"zip1 z4.d, z2.d, z3.d",
|
|
"zip2 z2.d, z2.d, z3.d",
|
|
"mov z1.q, z4.q[1]",
|
|
"mov z2.b, p6/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovhps xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x16 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v2.8b, v2.8b",
|
|
"ldr d3, [x4]",
|
|
"mov v2.d[1], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovhpd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x16 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v2.8b, v2.8b",
|
|
"ldr d3, [x4]",
|
|
"mov v2.d[1], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovshdup xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x16 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"trn2 v2.4s, v2.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovshdup ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x16 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"trn2 z2.s, z2.s, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovhps [rax], xmm0": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x17 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov v2.d[0], v2.d[1]",
|
|
"str d2, [x4]"
|
|
]
|
|
},
|
|
"vmovhpd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x17 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov v2.d[0], v2.d[1]",
|
|
"str d2, [x4]"
|
|
]
|
|
},
|
|
"vmovmskps rax, xmm0": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x50 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"ushr v2.4s, v2.4s, #31",
|
|
"index z3.s, #0, #1",
|
|
"ushl v2.4s, v2.4s, v3.4s",
|
|
"addv s2, v2.4s",
|
|
"mov w4, v2.s[0]"
|
|
]
|
|
},
|
|
"vmovmskps rax, ymm0": {
|
|
"ExpectedInstructionCount": 42,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x50 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov w20, #0x0",
|
|
"mov w21, v2.s[0]",
|
|
"lsr w21, w21, #31",
|
|
"orr x20, x20, x21",
|
|
"mov w21, v2.s[1]",
|
|
"lsr w21, w21, #31",
|
|
"lsl w21, w21, #1",
|
|
"orr x20, x20, x21",
|
|
"mov w21, v2.s[2]",
|
|
"lsr w21, w21, #31",
|
|
"lsl w21, w21, #2",
|
|
"orr x20, x20, x21",
|
|
"mov w21, v2.s[3]",
|
|
"lsr w21, w21, #31",
|
|
"lsl w21, w21, #3",
|
|
"orr x20, x20, x21",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z2.d",
|
|
"mov w21, v2.s[0]",
|
|
"lsr w21, w21, #31",
|
|
"lsl w21, w21, #4",
|
|
"orr x20, x20, x21",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z2.d",
|
|
"mov w21, v2.s[1]",
|
|
"lsr w21, w21, #31",
|
|
"lsl w21, w21, #5",
|
|
"orr x20, x20, x21",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z2.d",
|
|
"mov w21, v2.s[2]",
|
|
"lsr w21, w21, #31",
|
|
"lsl w21, w21, #6",
|
|
"orr x20, x20, x21",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z2.d",
|
|
"mov w21, v2.s[3]",
|
|
"lsr w21, w21, #31",
|
|
"lsl w21, w21, #7",
|
|
"orr x20, x20, x21",
|
|
"lsr w4, w20, #0"
|
|
]
|
|
},
|
|
"vmovmskpd rax, xmm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x50 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"uzp2 v2.4s, v2.4s, v2.4s",
|
|
"mov x20, v2.d[0]",
|
|
"bfi x20, x20, #31, #32",
|
|
"lsr x4, x20, #62"
|
|
]
|
|
},
|
|
"vmovmskpd rax, ymm0": {
|
|
"ExpectedInstructionCount": 22,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x50 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov w20, #0x0",
|
|
"mov x21, v2.d[0]",
|
|
"lsr x21, x21, #63",
|
|
"orr x20, x20, x21",
|
|
"mov x21, v2.d[1]",
|
|
"lsr x21, x21, #63",
|
|
"lsl x21, x21, #1",
|
|
"orr x20, x20, x21",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z2.d",
|
|
"mov x21, v2.d[0]",
|
|
"lsr x21, x21, #63",
|
|
"lsl x21, x21, #2",
|
|
"orr x20, x20, x21",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z2.d",
|
|
"mov x21, v2.d[1]",
|
|
"lsr x21, x21, #63",
|
|
"lsl x21, x21, #3",
|
|
"orr x20, x20, x21",
|
|
"lsr w4, w20, #0"
|
|
]
|
|
},
|
|
"vsqrtps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x51 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fsqrt v2.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsqrtps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x51 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fsqrt z2.s, p7/m, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsqrtpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x51 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fsqrt v2.2d, v2.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsqrtpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x51 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fsqrt z2.d, p7/m, z2.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsqrtss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b10 0x51 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z18.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"fsqrt s2, s2",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.s[0], v2.s[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsqrtsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b11 0x51 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z18.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"fsqrt d2, d2",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.d[0], v2.d[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vrsqrtps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"FEAT_FPRES could make this more optimal",
|
|
"Map 1 0b00 0x52 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fsqrt v1.4s, v2.4s",
|
|
"fdiv v2.4s, v0.4s, v1.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vrsqrtps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"FEAT_FPRES could make this more optimal",
|
|
"Map 1 0b00 0x52 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fsqrt z0.s, p7/m, z2.s",
|
|
"fmov z2.s, #0x70 (1.0000)",
|
|
"fdiv z2.s, p7/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vrsqrtss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"FEAT_FPRES could make this more optimal",
|
|
"Map 1 0b10 0x52 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z18.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"fmov s0, #0x70 (1.0000)",
|
|
"fsqrt s1, s2",
|
|
"fdiv s2, s0, s1",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.s[0], v2.s[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vrcpps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"FEAT_FPRES could make this more optimal",
|
|
"Map 1 0b00 0x53 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fdiv v2.4s, v0.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vrcpps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"FEAT_FPRES could make this more optimal",
|
|
"Map 1 0b00 0x53 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fmov z0.s, #0x70 (1.0000)",
|
|
"fdiv z0.s, p7/m, z0.s, z2.s",
|
|
"mov z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vrcpss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"FEAT_FPRES could make this more optimal",
|
|
"Map 1 0b10 0x53 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z18.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"fmov s0, #0x70 (1.0000)",
|
|
"fdiv s2, s0, s2",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.s[0], v2.s[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vandps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x54 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"and v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vandps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x54 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"and z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vandpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x54 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"and v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vandpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x54 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"and z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vandnps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x55 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"bic v2.16b, v3.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vandnps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x55 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"bic z2.d, z3.d, z2.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vandnpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x55 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"bic v2.16b, v3.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vandnpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x55 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"bic z2.d, z3.d, z2.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vorps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x56 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"orr v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vorps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x56 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"orr z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vorpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x56 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"orr v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vorpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x56 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"orr z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vxorps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x57 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vxorps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x57 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"eor z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vxorpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x57 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vxorpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x57 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"eor z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpcklbw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x60 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpcklbw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x60 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 z4.b, z2.b, z3.b",
|
|
"zip2 z2.b, z2.b, z3.b",
|
|
"mov z1.q, q2",
|
|
"mov z2.d, z4.d",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z2.b, p0/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpcklwd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x61 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpcklwd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x61 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 z4.h, z2.h, z3.h",
|
|
"zip2 z2.h, z2.h, z3.h",
|
|
"mov z1.q, q2",
|
|
"mov z2.d, z4.d",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z2.b, p0/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckldq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x62 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckldq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x62 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 z4.s, z2.s, z3.s",
|
|
"zip2 z2.s, z2.s, z3.s",
|
|
"mov z1.q, q2",
|
|
"mov z2.d, z4.d",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z2.b, p0/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpacksswb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x63 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqxtn v2.8b, v2.8h",
|
|
"sqxtn2 v2.16b, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpacksswb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x63 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqxtnb z1.b, z3.h",
|
|
"uzp1 z1.b, z1.b, z1.b",
|
|
"sqxtnb z2.b, z2.h",
|
|
"uzp1 z2.b, z2.b, z2.b",
|
|
"splice z2.b, p6, z2.b, z1.b",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpgtb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x64 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmgt v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpgtb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x64 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmpgt p0.b, p7/z, z2.b, z3.b",
|
|
"not z0.b, p0/m, z2.b",
|
|
"movprfx z2.b, p0/z, z2.b",
|
|
"orr z2.b, p0/m, z2.b, z0.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpgtw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x65 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmgt v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpgtw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x65 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmpgt p0.h, p7/z, z2.h, z3.h",
|
|
"not z0.h, p0/m, z2.h",
|
|
"movprfx z2.h, p0/z, z2.h",
|
|
"orr z2.h, p0/m, z2.h, z0.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpgtd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x66 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmgt v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpgtd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x66 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmpgt p0.s, p7/z, z2.s, z3.s",
|
|
"not z0.s, p0/m, z2.s",
|
|
"movprfx z2.s, p0/z, z2.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpackuswb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x67 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqxtun v2.8b, v2.8h",
|
|
"sqxtun2 v2.16b, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpackuswb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x67 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqxtunb z1.b, z3.h",
|
|
"uzp1 z1.b, z1.b, z1.b",
|
|
"sqxtunb z2.b, z2.h",
|
|
"uzp1 z2.b, z2.b, z2.b",
|
|
"splice z2.b, p6, z2.b, z1.b",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufd xmm0, xmm1, 00b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.s[0], v2.s[0]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.s[1], v2.s[0]",
|
|
"mov v3.s[2], v2.s[0]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.s[3], v2.s[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufd xmm0, xmm1, 01b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.s[0], v2.s[1]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.s[1], v2.s[0]",
|
|
"mov v3.s[2], v2.s[0]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.s[3], v2.s[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufd xmm0, xmm1, 10b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.s[0], v2.s[2]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.s[1], v2.s[0]",
|
|
"mov v3.s[2], v2.s[0]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.s[3], v2.s[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufd xmm0, xmm1, 11b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.s[0], v2.s[3]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.s[1], v2.s[0]",
|
|
"mov v3.s[2], v2.s[0]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.s[3], v2.s[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufd ymm0, ymm1, 00b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.s, s2",
|
|
"mov z3.d, z2.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-4",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #0",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-3",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #1",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-2",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #2",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-1",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #3",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufd ymm0, ymm1, 01b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.s, z2.s[1]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-4",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[5]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #0",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-3",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #1",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-2",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #2",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-1",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #3",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufd ymm0, ymm1, 10b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.s, z2.s[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-4",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[6]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #0",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-3",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #1",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-2",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #2",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-1",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #3",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufd ymm0, ymm1, 11b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.s, z2.s[3]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-4",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[7]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #0",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-3",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #1",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-2",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #2",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-1",
|
|
"mov z3.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #3",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufhw xmm0, xmm1, 00b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.h[4], v2.h[4]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.h[5], v2.h[4]",
|
|
"mov v3.h[6], v2.h[4]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.h[7], v2.h[4]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufhw xmm0, xmm1, 01b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.h[4], v2.h[5]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.h[5], v2.h[4]",
|
|
"mov v3.h[6], v2.h[4]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.h[7], v2.h[4]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufhw xmm0, xmm1, 10b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.h[4], v2.h[6]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.h[5], v2.h[4]",
|
|
"mov v3.h[6], v2.h[4]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.h[7], v2.h[4]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufhw xmm0, xmm1, 11b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.h[4], v2.h[7]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.h[5], v2.h[4]",
|
|
"mov v3.h[6], v2.h[4]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.h[7], v2.h[4]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufhw ymm0, ymm1, 00b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.h, z2.h[4]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-4",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #4",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-3",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #5",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-2",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #6",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-1",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #7",
|
|
"mov z2.h, p0/m, z1.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufhw ymm0, ymm1, 01b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.h, z2.h[5]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-4",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[13]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #4",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-3",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #5",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-2",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #6",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-1",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #7",
|
|
"mov z2.h, p0/m, z1.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufhw ymm0, ymm1, 10b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.h, z2.h[6]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-4",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[14]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #4",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-3",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #5",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-2",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #6",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-1",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #7",
|
|
"mov z2.h, p0/m, z1.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufhw ymm0, ymm1, 11b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.h, z2.h[7]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-4",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[15]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #4",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-3",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #5",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-2",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #6",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[4]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-1",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[12]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #7",
|
|
"mov z2.h, p0/m, z1.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshuflw xmm0, xmm1, 00b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.h[0], v2.h[0]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.h[1], v2.h[0]",
|
|
"mov v3.h[2], v2.h[0]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.h[3], v2.h[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshuflw xmm0, xmm1, 01b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.h[0], v2.h[1]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.h[1], v2.h[0]",
|
|
"mov v3.h[2], v2.h[0]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.h[3], v2.h[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshuflw xmm0, xmm1, 10b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.h[0], v2.h[2]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.h[1], v2.h[0]",
|
|
"mov v3.h[2], v2.h[0]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.h[3], v2.h[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshuflw xmm0, xmm1, 11b": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v0.16b, v2.16b",
|
|
"mov v0.h[0], v2.h[3]",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v3.h[1], v2.h[0]",
|
|
"mov v3.h[2], v2.h[0]",
|
|
"mov v0.16b, v3.16b",
|
|
"mov v0.h[3], v2.h[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshuflw ymm0, ymm1, 00b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.h, h2",
|
|
"mov z3.d, z2.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-8",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #0",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-7",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #1",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-6",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #2",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-5",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #3",
|
|
"mov z2.h, p0/m, z1.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshuflw ymm0, ymm1, 01b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.h, z2.h[1]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-8",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[9]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #0",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-7",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #1",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-6",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #2",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-5",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #3",
|
|
"mov z2.h, p0/m, z1.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshuflw ymm0, ymm1, 10b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.h, z2.h[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-8",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[10]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #0",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-7",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #1",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-6",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #2",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-5",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #3",
|
|
"mov z2.h, p0/m, z1.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshuflw ymm0, ymm1, 11b": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z1.h, z2.h[3]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-8",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[11]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #0",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-7",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #1",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-6",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #2",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, h2",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #-5",
|
|
"mov z3.h, p0/m, z1.h",
|
|
"mov z1.h, z2.h[8]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.h, #-8, #1",
|
|
"cmpeq p0.h, p7/z, z0.h, #3",
|
|
"mov z2.h, p0/m, z1.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpeqb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x74 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmeq v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpeqb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x74 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmpeq p0.b, p7/z, z2.b, z3.b",
|
|
"not z0.b, p0/m, z2.b",
|
|
"movprfx z2.b, p0/z, z2.b",
|
|
"orr z2.b, p0/m, z2.b, z0.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpeqw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x75 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmeq v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpeqw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x75 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmpeq p0.h, p7/z, z2.h, z3.h",
|
|
"not z0.h, p0/m, z2.h",
|
|
"movprfx z2.h, p0/z, z2.h",
|
|
"orr z2.h, p0/m, z2.h, z0.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpeqd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x76 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmeq v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpeqd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x76 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmpeq p0.s, p7/z, z2.s, z3.s",
|
|
"not z0.s, p0/m, z2.s",
|
|
"movprfx z2.s, p0/z, z2.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vzeroupper": {
|
|
"ExpectedInstructionCount": 48,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x77 L=0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z17.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z18.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z18.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z19.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z19.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z20.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z20.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z21.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z21.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z22.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z22.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z23.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z23.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z24.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z24.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z25.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z25.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z26.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z26.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z27.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z27.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z28.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z28.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z29.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z29.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z30.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z30.d, p7/m, z2.d",
|
|
"mov z2.d, p7/m, z31.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z31.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vzeroall": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Should use movi for all registers",
|
|
"Map 1 0b01 0x77 L=1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v2.2d, #0x0",
|
|
"mov z16.d, p7/m, z2.d",
|
|
"mov z17.d, p7/m, z2.d",
|
|
"mov z18.d, p7/m, z2.d",
|
|
"mov z19.d, p7/m, z2.d",
|
|
"mov z20.d, p7/m, z2.d",
|
|
"mov z21.d, p7/m, z2.d",
|
|
"mov z22.d, p7/m, z2.d",
|
|
"mov z23.d, p7/m, z2.d",
|
|
"mov z24.d, p7/m, z2.d",
|
|
"mov z25.d, p7/m, z2.d",
|
|
"mov z26.d, p7/m, z2.d",
|
|
"mov z27.d, p7/m, z2.d",
|
|
"mov z28.d, p7/m, z2.d",
|
|
"mov z29.d, p7/m, z2.d",
|
|
"mov z30.d, p7/m, z2.d",
|
|
"mov z31.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x00": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x00": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq p0.s, p7/z, z2.s, z3.s",
|
|
"not z0.s, p0/m, z2.s",
|
|
"movprfx z2.s, p0/z, z2.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x01": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt v2.4s, v3.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x01": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt p0.s, p7/z, z3.s, z2.s",
|
|
"not z0.s, p0/m, z3.s",
|
|
"movprfx z2.s, p0/z, z3.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x02": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge v2.4s, v3.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x02": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge p0.s, p7/z, z3.s, z2.s",
|
|
"not z0.s, p0/m, z3.s",
|
|
"movprfx z2.s, p0/z, z3.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x03": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge v0.4s, v2.4s, v3.4s",
|
|
"fcmgt v1.4s, v3.4s, v2.4s",
|
|
"orr v2.16b, v0.16b, v1.16b",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x03": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmuo p0.s, p7/z, z2.s, z3.s",
|
|
"not z0.s, p0/m, z2.s",
|
|
"movprfx z2.s, p0/z, z2.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x04": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq v2.4s, v2.4s, v3.4s",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x04": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmne p0.s, p7/z, z2.s, z3.s",
|
|
"not z0.s, p0/m, z2.s",
|
|
"movprfx z2.s, p0/z, z2.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x05": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt v2.4s, v3.4s, v2.4s",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x05": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt p0.s, p7/z, z3.s, z2.s",
|
|
"not z0.s, p0/m, z3.s",
|
|
"movprfx z2.s, p0/z, z3.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"not z2.b, p7/m, z2.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x06": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge v2.4s, v3.4s, v2.4s",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x06": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge p0.s, p7/z, z3.s, z2.s",
|
|
"not z0.s, p0/m, z3.s",
|
|
"movprfx z2.s, p0/z, z3.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"not z2.b, p7/m, z2.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x07": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge v0.4s, v2.4s, v3.4s",
|
|
"fcmgt v1.4s, v3.4s, v2.4s",
|
|
"orr v2.16b, v0.16b, v1.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x07": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmuo p0.s, p7/z, z2.s, z3.s",
|
|
"not p0.b, p7/z, p0.b",
|
|
"not z0.s, p0/m, z2.s",
|
|
"movprfx z2.s, p0/z, z2.s",
|
|
"orr z2.s, p0/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x00": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x00": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq p0.d, p7/z, z2.d, z3.d",
|
|
"not z0.d, p0/m, z2.d",
|
|
"movprfx z2.d, p0/z, z2.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x01": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt v2.2d, v3.2d, v2.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x01": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt p0.d, p7/z, z3.d, z2.d",
|
|
"not z0.d, p0/m, z3.d",
|
|
"movprfx z2.d, p0/z, z3.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x02": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge v2.2d, v3.2d, v2.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x02": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge p0.d, p7/z, z3.d, z2.d",
|
|
"not z0.d, p0/m, z3.d",
|
|
"movprfx z2.d, p0/z, z3.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x03": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge v0.2d, v2.2d, v3.2d",
|
|
"fcmgt v1.2d, v3.2d, v2.2d",
|
|
"orr v2.16b, v0.16b, v1.16b",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x03": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmuo p0.d, p7/z, z2.d, z3.d",
|
|
"not z0.d, p0/m, z2.d",
|
|
"movprfx z2.d, p0/z, z2.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x04": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq v2.2d, v2.2d, v3.2d",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x04": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmne p0.d, p7/z, z2.d, z3.d",
|
|
"not z0.d, p0/m, z2.d",
|
|
"movprfx z2.d, p0/z, z2.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x05": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt v2.2d, v3.2d, v2.2d",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x05": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt p0.d, p7/z, z3.d, z2.d",
|
|
"not z0.d, p0/m, z3.d",
|
|
"movprfx z2.d, p0/z, z3.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"not z2.b, p7/m, z2.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x06": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge v2.2d, v3.2d, v2.2d",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x06": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge p0.d, p7/z, z3.d, z2.d",
|
|
"not z0.d, p0/m, z3.d",
|
|
"movprfx z2.d, p0/z, z3.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"not z2.b, p7/m, z2.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x07": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge v0.2d, v2.2d, v3.2d",
|
|
"fcmgt v1.2d, v3.2d, v2.2d",
|
|
"orr v2.16b, v0.16b, v1.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x07": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmuo p0.d, p7/z, z2.d, z3.d",
|
|
"not p0.b, p7/z, p0.b",
|
|
"not z0.d, p0/m, z2.d",
|
|
"movprfx z2.d, p0/z, z2.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x00": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq s3, s2, s3",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x01": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt s3, s3, s2",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x02": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge s3, s3, s2",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x03": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge s0, s2, s3",
|
|
"fcmgt s1, s3, s2",
|
|
"orr v3.8b, v0.8b, v1.8b",
|
|
"mvn v3.8b, v3.8b",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x04": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq s3, s2, s3",
|
|
"mvn v3.8b, v3.8b",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x05": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt s3, s3, s2",
|
|
"mvn v3.16b, v3.16b",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x06": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge s3, s3, s2",
|
|
"mvn v3.16b, v3.16b",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x07": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge s0, s2, s3",
|
|
"fcmgt s1, s3, s2",
|
|
"orr v3.8b, v0.8b, v1.8b",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x00": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq d3, d2, d3",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x01": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt d3, d3, d2",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x02": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge d3, d3, d2",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x03": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge d0, d2, d3",
|
|
"fcmgt d1, d3, d2",
|
|
"orr v3.8b, v0.8b, v1.8b",
|
|
"mvn v3.8b, v3.8b",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x04": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmeq d3, d2, d3",
|
|
"mvn v3.8b, v3.8b",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x05": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt d3, d3, d2",
|
|
"mvn v3.16b, v3.16b",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x06": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge d3, d3, d2",
|
|
"mvn v3.16b, v3.16b",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x07": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmge d0, d2, d3",
|
|
"fcmgt d1, d3, d2",
|
|
"orr v3.8b, v0.8b, v1.8b",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpinsrw xmm0, xmm1, eax, 000b": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v2.h[0], w20",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpinsrw xmm0, xmm1, eax, 001b": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v2.h[1], w20",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpinsrw xmm0, xmm1, eax, 111b": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v2.h[7], w20",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpextrw eax, xmm0, 000b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"umov w20, v2.h[0]",
|
|
"uxth x4, w20"
|
|
]
|
|
},
|
|
"vpextrw eax, xmm0, 001b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"umov w20, v2.h[1]",
|
|
"uxth x4, w20"
|
|
]
|
|
},
|
|
"vpextrw eax, xmm0, 111b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"umov w20, v2.h[7]",
|
|
"uxth x4, w20"
|
|
]
|
|
},
|
|
"vshufps xmm0, xmm1, xmm2, 00b": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"dup v2.4s, v2.s[0]",
|
|
"dup v3.4s, v3.s[0]",
|
|
"zip1 v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufps ymm0, ymm1, ymm2, 00b": {
|
|
"ExpectedInstructionCount": 37,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.s, s2",
|
|
"mov z4.d, z2.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-4",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #0",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-3",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"mov z2.d, z4.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #1",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, s3",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-2",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, z3.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #2",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, s3",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-1",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, z3.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #3",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufps xmm0, xmm1, xmm2, 01b": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"ldr x0, [x28, #1640]",
|
|
"ldr q4, [x0, #16]",
|
|
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufps ymm0, ymm1, ymm2, 01b": {
|
|
"ExpectedInstructionCount": 37,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.s, z2.s[1]",
|
|
"mov z4.d, z2.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-4",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[5]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #0",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-3",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"mov z2.d, z4.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #1",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, s3",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-2",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, z3.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #2",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, s3",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-1",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, z3.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #3",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufps xmm0, xmm1, xmm2, 10b": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"ldr x0, [x28, #1640]",
|
|
"ldr q4, [x0, #32]",
|
|
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufps ymm0, ymm1, ymm2, 10b": {
|
|
"ExpectedInstructionCount": 37,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.s, z2.s[2]",
|
|
"mov z4.d, z2.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-4",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[6]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #0",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-3",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"mov z2.d, z4.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #1",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, s3",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-2",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, z3.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #2",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, s3",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-1",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, z3.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #3",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufps xmm0, xmm1, xmm2, 11b": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"ldr x0, [x28, #1640]",
|
|
"ldr q4, [x0, #48]",
|
|
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufps ymm0, ymm1, ymm2, 11b": {
|
|
"ExpectedInstructionCount": 37,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.s, z2.s[3]",
|
|
"mov z4.d, z2.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-4",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[7]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #0",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, s2",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-3",
|
|
"mov z4.s, p0/m, z1.s",
|
|
"mov z1.s, z2.s[4]",
|
|
"mov z2.d, z4.d",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #1",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, s3",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-2",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, z3.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #2",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, s3",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #-1",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z1.s, z3.s[4]",
|
|
"index z0.s, #-4, #1",
|
|
"cmpeq p0.s, p7/z, z0.s, #3",
|
|
"mov z2.s, p0/m, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufpd xmm0, xmm1, xmm2, 0b": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufpd ymm0, ymm1, ymm2, 0b": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.d, d2",
|
|
"mov z4.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-2",
|
|
"mov z4.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z2.d, z4.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z1.d, d3",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z1.d, z3.d[2]",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufpd xmm0, xmm1, xmm2, 1b": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"ext v2.16b, v2.16b, v3.16b, #8",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vshufpd ymm0, ymm1, ymm2, 1b": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z4.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-2",
|
|
"mov z4.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z2.d, z4.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z1.d, d3",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z1.d, z3.d[2]",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovaps xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x28 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovaps ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x28 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovaps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x29 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovaps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x29 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovapd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x28 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovapd ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x28 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovapd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x29 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovapd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x29 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovaps [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x29 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str q2, [x4]"
|
|
]
|
|
},
|
|
"vmovaps [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x29 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"st1b {z2.b}, p7, [x4]"
|
|
]
|
|
},
|
|
"vmovapd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x29 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str q2, [x4]"
|
|
]
|
|
},
|
|
"vmovapd [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x29 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"st1b {z2.b}, p7, [x4]"
|
|
]
|
|
},
|
|
"vcvtsi2ss xmm0, xmm1, eax": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"scvtf s3, w4",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtsi2ss xmm0, xmm1, rax": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"scvtf s3, x4",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtsi2sd xmm0, xmm1, eax": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"scvtf d3, w4",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtsi2sd xmm0, xmm1, rax": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"scvtf d3, x4",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovntps [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x2B 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str q2, [x4]"
|
|
]
|
|
},
|
|
"vmovntps [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x2B 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"st1b {z2.b}, p7, [x4]"
|
|
]
|
|
},
|
|
"vmovntpd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x2B 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str q2, [x4]"
|
|
]
|
|
},
|
|
"vmovntpd [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x2B 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"st1b {z2.b}, p7, [x4]"
|
|
]
|
|
},
|
|
"vcvttss2si eax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"fcvtzs w4, s2"
|
|
]
|
|
},
|
|
"vcvttss2si rax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"fcvtzs x4, s2"
|
|
]
|
|
},
|
|
"vcvttsd2si eax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"fcvtzs w4, d2"
|
|
]
|
|
},
|
|
"vcvttsd2si rax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"fcvtzs x4, d2"
|
|
]
|
|
},
|
|
"vcvtss2si eax, xmm0": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"frinti s0, s2",
|
|
"fcvtzs w4, s0"
|
|
]
|
|
},
|
|
"vcvtss2si rax, xmm0": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"frinti s0, s2",
|
|
"fcvtzs x4, s0"
|
|
]
|
|
},
|
|
"vcvtsd2si eax, xmm0": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"frinti d0, d2",
|
|
"fcvtzs x4, d0"
|
|
]
|
|
},
|
|
"vcvtsd2si rax, xmm0": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"frinti d0, d2",
|
|
"fcvtzs x4, d0"
|
|
]
|
|
},
|
|
"vucomiss xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x2e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"fcmp s2, s3",
|
|
"cset x20, eq",
|
|
"csinc x20, x20, xzr, vc",
|
|
"cset x1, lt",
|
|
"bfi x20, x1, #1, #1",
|
|
"cset x1, vs",
|
|
"bfi x20, x1, #2, #1",
|
|
"ubfx x21, x20, #1, #1",
|
|
"ubfx x22, x20, #0, #1",
|
|
"ubfx x20, x20, #2, #1",
|
|
"lsl x21, x21, #29",
|
|
"orr w21, w21, w22, lsl #30",
|
|
"eor w20, w20, #0x1",
|
|
"strb w20, [x28, #706]",
|
|
"mov w20, #0x0",
|
|
"mov w22, #0x90000000",
|
|
"bic x21, x21, x22",
|
|
"strb w20, [x28, #708]",
|
|
"str w21, [x28, #728]"
|
|
]
|
|
},
|
|
"vucomisd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 24,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x2e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"fcmp d2, d3",
|
|
"cset x20, eq",
|
|
"csinc x20, x20, xzr, vc",
|
|
"cset x1, lt",
|
|
"bfi x20, x1, #1, #1",
|
|
"cset x1, vs",
|
|
"bfi x20, x1, #2, #1",
|
|
"ubfx x21, x20, #1, #1",
|
|
"ubfx x22, x20, #0, #1",
|
|
"ubfx x20, x20, #2, #1",
|
|
"ldr w23, [x28, #728]",
|
|
"mov w0, w23",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"bfi w21, w22, #30, #1",
|
|
"eor w20, w20, #0x1",
|
|
"strb w20, [x28, #706]",
|
|
"mov w20, #0x0",
|
|
"mov w22, #0x90000000",
|
|
"bic x21, x21, x22",
|
|
"strb w20, [x28, #708]",
|
|
"str w21, [x28, #728]"
|
|
]
|
|
},
|
|
"vcomiss xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 24,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x2f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"fcmp s2, s3",
|
|
"cset x20, eq",
|
|
"csinc x20, x20, xzr, vc",
|
|
"cset x1, lt",
|
|
"bfi x20, x1, #1, #1",
|
|
"cset x1, vs",
|
|
"bfi x20, x1, #2, #1",
|
|
"ubfx x21, x20, #1, #1",
|
|
"ubfx x22, x20, #0, #1",
|
|
"ubfx x20, x20, #2, #1",
|
|
"ldr w23, [x28, #728]",
|
|
"mov w0, w23",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"bfi w21, w22, #30, #1",
|
|
"eor w20, w20, #0x1",
|
|
"strb w20, [x28, #706]",
|
|
"mov w20, #0x0",
|
|
"mov w22, #0x90000000",
|
|
"bic x21, x21, x22",
|
|
"strb w20, [x28, #708]",
|
|
"str w21, [x28, #728]"
|
|
]
|
|
},
|
|
"vcomisd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 24,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x2f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"fcmp d2, d3",
|
|
"cset x20, eq",
|
|
"csinc x20, x20, xzr, vc",
|
|
"cset x1, lt",
|
|
"bfi x20, x1, #1, #1",
|
|
"cset x1, vs",
|
|
"bfi x20, x1, #2, #1",
|
|
"ubfx x21, x20, #1, #1",
|
|
"ubfx x22, x20, #0, #1",
|
|
"ubfx x20, x20, #2, #1",
|
|
"ldr w23, [x28, #728]",
|
|
"mov w0, w23",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"bfi w21, w22, #30, #1",
|
|
"eor w20, w20, #0x1",
|
|
"strb w20, [x28, #706]",
|
|
"mov w20, #0x0",
|
|
"mov w22, #0x90000000",
|
|
"bic x21, x21, x22",
|
|
"strb w20, [x28, #708]",
|
|
"str w21, [x28, #728]"
|
|
]
|
|
},
|
|
"vaddps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fadd v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaddps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x58 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fadd z2.s, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaddpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fadd v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaddpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x58 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fadd z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaddss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fadd s3, s2, s3",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaddsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fadd d3, d2, d3",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmulps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fmul v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmulps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x59 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fmul z2.s, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmulpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fmul v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmulpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x59 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fmul z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmulss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fmul s3, s2, s3",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmulsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fmul d3, d2, d3",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtps2pd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fcvtl v2.2d, v2.2s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtpd2ps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fcvtn v2.2s, v2.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtss2sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcvt d3, s3",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtsd2ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcvt s3, d3",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtdq2ps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"scvtf v2.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtdq2ps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"scvtf z2.s, p7/m, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtps2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"frinti v2.4s, v2.4s",
|
|
"fcvtzs v2.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtps2dq ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"frinti z2.s, p7/m, z2.s",
|
|
"fcvtzs z2.s, p7/m, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvttps2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x5b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fcvtzs v2.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvttps2dq ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x5b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fcvtzs z2.s, p7/m, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsubps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fsub v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsubps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fsub z2.s, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsubpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fsub v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsubpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fsub z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsubss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x5c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fsub s3, s2, s3",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vsubsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x5c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fsub d3, d2, d3",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vminps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt v0.4s, v3.4s, v2.4s",
|
|
"bif v2.16b, v3.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vminps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt p0.s, p7/z, z3.s, z2.s",
|
|
"not p0.b, p7/z, p0.b",
|
|
"mov z2.s, p0/m, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vminpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt v0.2d, v3.2d, v2.2d",
|
|
"bif v2.16b, v3.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vminpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt p0.d, p7/z, z3.d, z2.d",
|
|
"not p0.b, p7/z, p0.b",
|
|
"mov z2.d, p0/m, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vminss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x5d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmp s2, s3",
|
|
"fcsel s3, s2, s3, mi",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vminsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x5d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmp d2, d3",
|
|
"fcsel d3, d2, d3, mi",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vdivps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fdiv v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vdivps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fdiv z2.s, p7/m, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vdivpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fdiv v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vdivpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fdiv z2.d, p7/m, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vdivss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x5e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fdiv s3, s2, s3",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vdivsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x5e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fdiv d3, d2, d3",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaxps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt v0.4s, v3.4s, v2.4s",
|
|
"bit v2.16b, v3.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaxps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b00 0x5f 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt p0.s, p7/z, z3.s, z2.s",
|
|
"mov z2.s, p0/m, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaxpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt v0.2d, v3.2d, v2.2d",
|
|
"bit v2.16b, v3.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaxpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x5f 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmgt p0.d, p7/z, z3.d, z2.d",
|
|
"mov z2.d, p0/m, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaxss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x5f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmp s2, s3",
|
|
"fcsel s3, s3, s2, mi",
|
|
"mov v2.s[0], v3.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaxsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x5f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"fcmp d2, d3",
|
|
"fcsel d3, d3, d2, mi",
|
|
"mov v2.d[0], v3.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckhbw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x68 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip2 v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckhbw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x68 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 z4.b, z2.b, z3.b",
|
|
"zip2 z2.b, z2.b, z3.b",
|
|
"mov z1.q, z4.q[1]",
|
|
"mov z2.b, p6/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckhwd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x69 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip2 v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckhwd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x69 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 z4.h, z2.h, z3.h",
|
|
"zip2 z2.h, z2.h, z3.h",
|
|
"mov z1.q, z4.q[1]",
|
|
"mov z2.b, p6/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckhdq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip2 v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckhdq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6a 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 z4.s, z2.s, z3.s",
|
|
"zip2 z2.s, z2.s, z3.s",
|
|
"mov z1.q, z4.q[1]",
|
|
"mov z2.b, p6/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpackssdw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqxtn v2.4h, v2.4s",
|
|
"sqxtn2 v2.8h, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpackssdw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqxtnb z1.h, z3.s",
|
|
"uzp1 z1.h, z1.h, z1.h",
|
|
"sqxtnb z2.h, z2.s",
|
|
"uzp1 z2.h, z2.h, z2.h",
|
|
"splice z2.h, p6, z2.h, z1.h",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpcklqdq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpcklqdq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 z4.d, z2.d, z3.d",
|
|
"zip2 z2.d, z2.d, z3.d",
|
|
"mov z1.q, q2",
|
|
"mov z2.d, z4.d",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z2.b, p0/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckhqdq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip2 v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpunpckhqdq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"zip1 z4.d, z2.d, z3.d",
|
|
"zip2 z2.d, z2.d, z3.d",
|
|
"mov z1.q, z4.q[1]",
|
|
"mov z2.b, p6/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovd xmm0, dword [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovq xmm0, qword [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovdqa xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovdqa [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x6f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str q2, [x4]"
|
|
]
|
|
},
|
|
"vmovdqu xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x6f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovdqu [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x6f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str q2, [x4]"
|
|
]
|
|
},
|
|
"vhaddpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x7c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"faddp v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vhaddpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x7c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movprfx z0, z2",
|
|
"faddp z0.d, p7/m, z0.d, z3.d",
|
|
"uzp1 z2.d, z0.d, z0.d",
|
|
"uzp2 z1.d, z0.d, z0.d",
|
|
"splice z2.d, p6, z2.d, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vhaddps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x7c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"faddp v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vhaddps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x7c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movprfx z0, z2",
|
|
"faddp z0.s, p7/m, z0.s, z3.s",
|
|
"uzp1 z2.s, z0.s, z0.s",
|
|
"uzp2 z1.s, z0.s, z0.s",
|
|
"splice z2.d, p6, z2.d, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vhsubpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x7d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 v4.2d, v2.2d, v3.2d",
|
|
"uzp2 v2.2d, v2.2d, v3.2d",
|
|
"fsub v2.2d, v4.2d, v2.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vhsubpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x7d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 z4.d, z2.d, z3.d",
|
|
"uzp2 z2.d, z2.d, z3.d",
|
|
"fsub z2.d, z4.d, z2.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vhsubps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x7d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 v4.4s, v2.4s, v3.4s",
|
|
"uzp2 v2.4s, v2.4s, v3.4s",
|
|
"fsub v2.4s, v4.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vhsubps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0x7d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 z4.s, z2.s, z3.s",
|
|
"uzp2 z2.s, z2.s, z3.s",
|
|
"fsub z2.s, z4.s, z2.s",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovd dword [rax], xmm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x7e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"movi v0.2d, #0x0",
|
|
"mov v0.s[0], v2.s[0]",
|
|
"mov v2.16b, v0.16b",
|
|
"str s2, [x4]"
|
|
]
|
|
},
|
|
"vmovq qword [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x7e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str d2, [x4]"
|
|
]
|
|
},
|
|
"vmovdqa ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x7f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovdqa [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0x7f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"st1b {z2.b}, p7, [x4]"
|
|
]
|
|
},
|
|
"vmovdqu ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x7f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovdqu [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0x7f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"st1b {z2.b}, p7, [x4]"
|
|
]
|
|
},
|
|
"vaddsubpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd0 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"ldr x0, [x28, #1584]",
|
|
"ldr q4, [x0]",
|
|
"eor v3.16b, v3.16b, v4.16b",
|
|
"fadd v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaddsubpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"ldr x0, [x28, #1584]",
|
|
"ld1b {z4.b}, p7/z, [x0]",
|
|
"eor z3.d, z3.d, z4.d",
|
|
"fadd z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaddsubps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xd0 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"ldr x0, [x28, #1568]",
|
|
"ldr q4, [x0]",
|
|
"eor v3.16b, v3.16b, v4.16b",
|
|
"fadd v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaddsubps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xd0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"ldr x0, [x28, #1568]",
|
|
"ld1b {z4.b}, p7/z, [x0]",
|
|
"eor z3.d, z3.d, z4.d",
|
|
"fadd z2.s, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrlw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd1 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsr z2.h, p6/m, z2.h, z0.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrlw ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd1 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsr z2.h, p7/m, z2.h, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrld xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsr z2.s, p6/m, z2.s, z0.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrld ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsr z2.s, p7/m, z2.s, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrlq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd3 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsr z2.d, p6/m, z2.d, z0.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrlq ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd3 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsr z2.d, p7/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"add v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd4 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"add z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmullw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mul v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmullw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd4 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mul z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovq [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str d2, [x4]"
|
|
]
|
|
},
|
|
"vpmovmskb rax, xmm0": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd7 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov x20, #0x201",
|
|
"movk x20, #0x804, lsl #16",
|
|
"movk x20, #0x2010, lsl #32",
|
|
"movk x20, #0x8040, lsl #48",
|
|
"dup v3.2d, x20",
|
|
"cmlt v2.16b, v2.16b, #0",
|
|
"and v2.16b, v2.16b, v3.16b",
|
|
"addp v2.16b, v2.16b, v2.16b",
|
|
"addp v2.8b, v2.8b, v2.8b",
|
|
"addp v2.8b, v2.8b, v2.8b",
|
|
"umov w4, v2.h[0]"
|
|
]
|
|
},
|
|
"vpmovmskb rax, ymm0": {
|
|
"ExpectedInstructionCount": 20,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd7 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov x20, #0x201",
|
|
"movk x20, #0x804, lsl #16",
|
|
"movk x20, #0x2010, lsl #32",
|
|
"movk x20, #0x8040, lsl #48",
|
|
"mov z3.d, x20",
|
|
"mov z0.d, #0",
|
|
"cmplt p0.b, p7/z, z2.b, #0",
|
|
"not z0.b, p0/m, z2.b",
|
|
"orr z0.b, p0/m, z0.b, z2.b",
|
|
"mov z2.d, z0.d",
|
|
"and z2.d, z2.d, z3.d",
|
|
"movprfx z0, z2",
|
|
"addp z0.b, p7/m, z0.b, z2.b",
|
|
"uzp1 z2.b, z0.b, z0.b",
|
|
"uzp2 z1.b, z0.b, z0.b",
|
|
"splice z2.d, p6, z2.d, z1.d",
|
|
"addp v2.16b, v2.16b, v2.16b",
|
|
"addp v2.8b, v2.8b, v2.8b",
|
|
"mov w4, v2.s[0]"
|
|
]
|
|
},
|
|
"vpsubusb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd8 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uqsub v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubusb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd8 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uqsub z2.b, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubusw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd9 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uqsub v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubusw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xd9 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uqsub z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminub xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xda 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umin v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminub ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xda 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umin z2.b, p7/m, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpand xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xdb 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"and v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpand ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xdb 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"and z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddusb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xdc 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uqadd v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddusb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xdc 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uqadd z2.b, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddusw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xdd 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uqadd v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddusw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xdd 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uqadd z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxub xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xdd 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umax v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxub ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xde 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umax z2.b, p7/m, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpandn xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xdf 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"bic v2.16b, v3.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpandn ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xdf 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"bic z2.d, z3.d, z2.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpavgb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe0 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"urhadd v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpavgb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"urhadd z2.b, p7/m, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsraw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe1 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"asr z2.h, p6/m, z2.h, z0.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsraw ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe1 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"asr z2.h, p7/m, z2.h, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrad xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"asr z2.s, p6/m, z2.s, z0.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrad ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"asr z2.s, p7/m, z2.s, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpavgw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe3 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"urhadd v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpavgw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe3 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"urhadd z2.h, p7/m, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmulhuw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umulh z2.h, p6/m, z2.h, z3.h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmulhuw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe4 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umulh z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmulhw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smulh z2.h, p6/m, z2.h, z3.h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmulhw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe5 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smulh z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvttpd2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fcvtn v2.2s, v2.2d",
|
|
"fcvtzs v2.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvttpd2dq xmm0, ymm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fcvtnt z2.s, p7/m, z2.d",
|
|
"uzp2 z2.s, z2.s, z2.s",
|
|
"fcvtzs z2.s, p7/m, z2.s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtdq2pd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xe6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sxtl v2.2d, v2.2s",
|
|
"scvtf v2.2d, v2.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtdq2pd ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b10 0xe6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sunpklo z2.d, z2.s",
|
|
"scvtf z2.d, p7/m, z2.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtpd2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xe6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fcvtn v2.2s, v2.2d",
|
|
"frinti v2.4s, v2.4s",
|
|
"fcvtzs v2.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vcvtpd2dq xmm0, ymm1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xe6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"fcvtnt z2.s, p7/m, z2.d",
|
|
"uzp2 z2.s, z2.s, z2.s",
|
|
"frinti z2.s, p7/m, z2.s",
|
|
"fcvtzs z2.s, p7/m, z2.s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovntdq [rax], xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe7 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"str q2, [x4]"
|
|
]
|
|
},
|
|
"vmovntdq [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe7 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"st1b {z2.b}, p7, [x4]"
|
|
]
|
|
},
|
|
"vpsubsb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe8 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqsub v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubsb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe8 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqsub z2.b, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe9 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqsub v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xe9 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqsub z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xea 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smin v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xea 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smin z2.h, p7/m, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpor xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xeb 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"orr v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpor ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xeb 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"orr z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddsb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xec 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqadd v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddsb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xec 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqadd z2.b, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xed 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqadd v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xed 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqadd z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xee 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smax v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xee 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smax z2.h, p7/m, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpxor xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xef 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpxor ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xef 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"eor z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vlddqu xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xf0 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vlddqu ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b11 0xf0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsllw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf1 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsl z2.h, p6/m, z2.h, z0.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsllw ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf1 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsl z2.h, p7/m, z2.h, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpslld xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsl z2.s, p6/m, z2.s, z0.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpslld ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsl z2.s, p7/m, z2.s, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsllq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf3 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsl z2.d, p6/m, z2.d, z0.d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsllq ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf3 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.d, d3",
|
|
"lsl z2.d, p7/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmuludq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 v2.4s, v2.4s, v2.4s",
|
|
"uzp1 v3.4s, v3.4s, v3.4s",
|
|
"umull v2.2d, v2.2s, v3.2s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmuludq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf4 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 z2.s, z2.s, z2.s",
|
|
"uzp1 z3.s, z3.s, z3.s",
|
|
"umullb z0.d, z2.s, z3.s",
|
|
"umullt z1.d, z2.s, z3.s",
|
|
"zip1 z2.d, z0.d, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaddwd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smull v4.4s, v2.4h, v3.4h",
|
|
"smull2 v2.4s, v2.8h, v3.8h",
|
|
"addp v2.4s, v4.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaddwd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf5 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smullb z0.s, z2.h, z3.h",
|
|
"smullt z1.s, z2.h, z3.h",
|
|
"zip1 z4.s, z0.s, z1.s",
|
|
"smullb z0.s, z2.h, z3.h",
|
|
"smullt z1.s, z2.h, z3.h",
|
|
"zip2 z2.s, z0.s, z1.s",
|
|
"movprfx z0, z4",
|
|
"addp z0.s, p7/m, z0.s, z2.s",
|
|
"uzp1 z2.s, z0.s, z0.s",
|
|
"uzp2 z1.s, z0.s, z0.s",
|
|
"splice z2.d, p6, z2.d, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsadbw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uabdl v4.8h, v2.8b, v3.8b",
|
|
"uabdl2 v2.8h, v2.16b, v3.16b",
|
|
"addv h3, v4.8h",
|
|
"addv h2, v2.8h",
|
|
"zip1 v2.2d, v3.2d, v2.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsadbw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 35,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uabdlb z0.h, z2.b, z3.b",
|
|
"uabdlt z1.h, z2.b, z3.b",
|
|
"zip1 z4.h, z0.h, z1.h",
|
|
"uabdlb z0.h, z2.b, z3.b",
|
|
"uabdlt z1.h, z2.b, z3.b",
|
|
"zip2 z2.h, z0.h, z1.h",
|
|
"addv h3, v4.8h",
|
|
"addv h5, v2.8h",
|
|
"zip1 z3.d, z3.d, z5.d",
|
|
"mov z4.q, z4.q[1]",
|
|
"mov z2.q, z2.q[1]",
|
|
"addv h4, v4.8h",
|
|
"addv h2, v2.8h",
|
|
"mov z1.d, d2",
|
|
"mov z2.d, z4.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z1.q, q2",
|
|
"mov z2.d, z3.d",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z2.b, p0/m, z1.b",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaskmovdqu xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf7 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"cmlt v2.16b, v2.16b, #0",
|
|
"mov z3.d, p7/m, z16.d",
|
|
"ldr q4, [x11]",
|
|
"bsl v2.16b, v3.16b, v4.16b",
|
|
"str q2, [x11]"
|
|
]
|
|
},
|
|
"vpsubb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf8 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sub v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf8 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sub z2.b, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf9 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sub v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xf9 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sub z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfa 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sub v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfa 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sub z2.s, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfb 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sub v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsubq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfb 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sub z2.d, z2.d, z3.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfc 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"add v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfc 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"add z2.b, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfd 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"add v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfd 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"add z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfe 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"add v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpaddd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 1 0b01 0xfe 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"add z2.s, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
}
|
|
}
|
|
}
|