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FEX-Emu--FEX/unittests/InstructionCountCI/Secondary_32Bit.json
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2026-09-21 14:56:47 -07:00

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{
"Features": {
"Bitness": 32,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"AFP"
],
"BinaryCacheVersion": 26
},
"Instructions": {
"push fs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #970]",
"str w20, [x8, #-4]!"
]
},
"pop fs": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xa1",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #970]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #1000]"
]
},
"push gs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #968]",
"str w20, [x8, #-4]!"
]
},
"pop gs": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xa9",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #968]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #992]"
]
}
}
}