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FEX-Emu--FEX/unittests/InstructionCountCI/AVX128/VEX_map3.json
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Ryan Houdek 0a41f470f8 InstcountCI: Update
2026-09-21 14:56:47 -07:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"AFP",
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 26
},
"Instructions": {
"vpermq ymm0, ymm1, 1": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ext v16.16b, v17.16b, v17.16b, #8",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"zip1 v16.2d, v2.2d, v17.2d",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 3": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ext v16.16b, v2.16b, v17.16b, #8",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 4": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpermq ymm0, ymm1, 5": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"dup v16.2d, v17.d[1]",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 6": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[1]",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 7": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"trn2 v16.2d, v2.2d, v17.2d",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 8": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"zip1 v16.2d, v17.2d, v2.2d",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 9": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ext v16.16b, v17.16b, v2.16b, #8",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 10": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v2.d[0]",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 11": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ext v16.16b, v2.16b, v2.16b, #8",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 12": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mov v16.16b, v17.16b",
"mov v16.d[1], v2.d[1]",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 13": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"trn2 v16.2d, v17.2d, v2.2d",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 14": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 15": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v2.d[1]",
"dup v2.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"dup v16.2d, v17.d[0]",
"str q16, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 01010101b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"dup v16.2d, v17.d[1]",
"str q16, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 10101010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v2.d[0]",
"str q16, [x28, #192]"
]
},
"vpermq ymm0, ymm1, 11111111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v2.d[1]",
"str q16, [x28, #192]"
]
},
"vpermpd ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x01 256-bit"
],
"ExpectedArm64ASM": [
"dup v16.2d, v17.d[0]",
"str q16, [x28, #192]"
]
},
"vpermpd ymm0, ymm1, 01010101b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x01 256-bit"
],
"ExpectedArm64ASM": [
"dup v16.2d, v17.d[1]",
"str q16, [x28, #192]"
]
},
"vpermpd ymm0, ymm1, 10101010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x01 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v2.d[0]",
"str q16, [x28, #192]"
]
},
"vpermpd ymm0, ymm1, 11111111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x01 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v2.d[1]",
"str q16, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 0000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 0001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.s[0], v17.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 0010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.s[1], v17.s[1]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 0011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.d[0], v17.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 0100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.s[2], v17.s[2]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 0101b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"rev64 v2.4s, v17.4s",
"trn2 v16.4s, v2.4s, v16.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 0110b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3328]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 0111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3344]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 1000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.s[3], v17.s[3]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 1001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3360]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 1010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"rev64 v2.4s, v16.4s",
"trn2 v16.4s, v2.4s, v17.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 1011b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3376]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 1100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.d[1], v17.d[1]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 1101b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3392]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 1110b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3408]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendd xmm0, xmm1, 1111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpblendd ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x02 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"str q2, [x28, #192]"
]
},
"vpblendd ymm0, ymm1, 01010101b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x02 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"rev64 v4.4s, v17.4s",
"trn2 v16.4s, v4.4s, v16.4s",
"rev64 v3.4s, v3.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"str q2, [x28, #192]"
]
},
"vpblendd ymm0, ymm1, 10101010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x02 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"rev64 v4.4s, v16.4s",
"trn2 v16.4s, v4.4s, v17.4s",
"rev64 v2.4s, v2.4s",
"trn2 v2.4s, v2.4s, v3.4s",
"str q2, [x28, #192]"
]
},
"vpblendd ymm0, ymm1, 11111111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x02 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpermilps xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x03 128-bit"
],
"ExpectedArm64ASM": [
"dup v16.4s, v17.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpermilps xmm0, xmm1, 01010101b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x03 128-bit"
],
"ExpectedArm64ASM": [
"dup v16.4s, v17.s[1]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpermilps xmm0, xmm1, 10101010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x03 128-bit"
],
"ExpectedArm64ASM": [
"dup v16.4s, v17.s[2]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpermilps xmm0, xmm1, 11111111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x03 128-bit"
],
"ExpectedArm64ASM": [
"dup v16.4s, v17.s[3]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpermilps ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x03 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.4s, v17.s[0]",
"dup v2.4s, v2.s[0]",
"str q2, [x28, #192]"
]
},
"vpermilps ymm0, ymm1, 01010101b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x03 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.4s, v17.s[1]",
"dup v2.4s, v2.s[1]",
"str q2, [x28, #192]"
]
},
"vpermilps ymm0, ymm1, 10101010b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x03 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.4s, v17.s[2]",
"dup v2.4s, v2.s[2]",
"str q2, [x28, #192]"
]
},
"vpermilps ymm0, ymm1, 11111111b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x03 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.4s, v17.s[3]",
"dup v2.4s, v2.s[3]",
"str q2, [x28, #192]"
]
},
"vpermilpd xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x05 128-bit"
],
"ExpectedArm64ASM": [
"dup v16.2d, v17.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpermilpd xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x05 128-bit"
],
"ExpectedArm64ASM": [
"ext v16.16b, v17.16b, v17.16b, #8",
"stp xzr, xzr, [x28, #192]"
]
},
"vpermilpd xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x05 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpermilpd xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x05 128-bit"
],
"ExpectedArm64ASM": [
"dup v16.2d, v17.d[1]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 0000b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v17.d[0]",
"dup v2.2d, v2.d[0]",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 0001b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ext v16.16b, v17.16b, v17.16b, #8",
"dup v2.2d, v2.d[0]",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 0010b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v2.2d, v2.d[0]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpermilpd ymm0, ymm1, 0011b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v17.d[1]",
"dup v2.2d, v2.d[0]",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 0100b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v17.d[0]",
"ext v2.16b, v2.16b, v2.16b, #8",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 0101b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ext v16.16b, v17.16b, v17.16b, #8",
"ext v2.16b, v2.16b, v2.16b, #8",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 0110b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ext v2.16b, v2.16b, v2.16b, #8",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpermilpd ymm0, ymm1, 0111b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v17.d[1]",
"ext v2.16b, v2.16b, v2.16b, #8",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 1000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v17.d[0]",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 1001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ext v16.16b, v17.16b, v17.16b, #8",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 1010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpermilpd ymm0, ymm1, 1011b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v17.d[1]",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 1100b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v17.d[0]",
"dup v2.2d, v2.d[1]",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 1101b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ext v16.16b, v17.16b, v17.16b, #8",
"dup v2.2d, v2.d[1]",
"str q2, [x28, #192]"
]
},
"vpermilpd ymm0, ymm1, 1110b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v2.2d, v2.d[1]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpermilpd ymm0, ymm1, 1111b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"dup v16.2d, v17.d[1]",
"dup v2.2d, v2.d[1]",
"str q2, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"str q17, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"str q17, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"str q17, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #224]",
"str q17, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"str q16, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010011b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q16, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"str q18, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #224]",
"str q18, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"ldr q2, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #224]",
"str q16, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00001000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"str q17, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00011000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"movi v16.2d, #0x0",
"str q2, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00101000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"str q18, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00111000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"movi v16.2d, #0x0",
"str q2, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10001000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"stp xzr, xzr, [x28, #192]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundps xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frintn v16.4s, v17.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundps xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frintm v16.4s, v17.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundps xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frintp v16.4s, v17.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundps xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frintz v16.4s, v17.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundps xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frinti v16.4s, v17.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundps ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 4,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frintn v16.4s, v17.4s",
"frintn v2.4s, v2.4s",
"str q2, [x28, #192]"
]
},
"vroundps ymm0, ymm1, 00000001b": {
"ExpectedInstructionCount": 4,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frintm v16.4s, v17.4s",
"frintm v2.4s, v2.4s",
"str q2, [x28, #192]"
]
},
"vroundps ymm0, ymm1, 00000010b": {
"ExpectedInstructionCount": 4,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frintp v16.4s, v17.4s",
"frintp v2.4s, v2.4s",
"str q2, [x28, #192]"
]
},
"vroundps ymm0, ymm1, 00000011b": {
"ExpectedInstructionCount": 4,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frintz v16.4s, v17.4s",
"frintz v2.4s, v2.4s",
"str q2, [x28, #192]"
]
},
"vroundps ymm0, ymm1, 00000100b": {
"ExpectedInstructionCount": 4,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frinti v16.4s, v17.4s",
"frinti v2.4s, v2.4s",
"str q2, [x28, #192]"
]
},
"vroundpd xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frintn v16.2d, v17.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundpd xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frintm v16.2d, v17.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundpd xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frintp v16.2d, v17.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundpd xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frintz v16.2d, v17.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundpd xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frinti v16.2d, v17.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundpd ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 4,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frintn v16.2d, v17.2d",
"frintn v2.2d, v2.2d",
"str q2, [x28, #192]"
]
},
"vroundpd ymm0, ymm1, 00000001b": {
"ExpectedInstructionCount": 4,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frintm v16.2d, v17.2d",
"frintm v2.2d, v2.2d",
"str q2, [x28, #192]"
]
},
"vroundpd ymm0, ymm1, 00000010b": {
"ExpectedInstructionCount": 4,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frintp v16.2d, v17.2d",
"frintp v2.2d, v2.2d",
"str q2, [x28, #192]"
]
},
"vroundpd ymm0, ymm1, 00000011b": {
"ExpectedInstructionCount": 4,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frintz v16.2d, v17.2d",
"frintz v2.2d, v2.2d",
"str q2, [x28, #192]"
]
},
"vroundpd ymm0, ymm1, 00000100b": {
"ExpectedInstructionCount": 4,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"frinti v16.2d, v17.2d",
"frinti v2.2d, v2.2d",
"str q2, [x28, #192]"
]
},
"vroundss xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"frintn s0, s17",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundss xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"frintm s0, s17",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundss xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"frintp s0, s17",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundss xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 3,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"frintz s0, s17",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundss xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 3,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"frinti s0, s17",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundsd xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"frintn d0, d17",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundsd xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"frintm d0, d17",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundsd xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"frintp d0, d17",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundsd xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 3,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"frintz d0, d17",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vroundsd xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 3,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"frinti d0, d17",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vblendps xmm0, xmm1, xmm2, 0000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0c 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vblendps xmm0, xmm1, xmm2, 0001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0c 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[0], v18.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vblendps xmm0, xmm1, xmm2, 1111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0c 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vblendps ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0c 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vblendps ymm0, ymm1, ymm2, 10000001b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x0c 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v16.16b, v17.16b",
"mov v16.s[0], v18.s[0]",
"mov v2.s[3], v3.s[3]",
"str q2, [x28, #192]"
]
},
"vblendps ymm0, ymm1, ymm2, 11111111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0c 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vblendpd xmm0, xmm1, xmm2, 00b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0d 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vblendpd xmm0, xmm1, xmm2, 01b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0d 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.d[0], v18.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vblendpd xmm0, xmm1, xmm2, 10b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0d 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.d[1], v18.d[1]",
"stp xzr, xzr, [x28, #192]"
]
},
"vblendpd xmm0, xmm1, xmm2, 11b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0d 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vblendpd ymm0, ymm1, ymm2, 0000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vblendpd ymm0, ymm1, ymm2, 0001b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mov v16.16b, v17.16b",
"mov v16.d[0], v18.d[0]",
"str q2, [x28, #192]"
]
},
"vblendpd ymm0, ymm1, ymm2, 0010b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mov v16.16b, v17.16b",
"mov v16.d[1], v18.d[1]",
"str q2, [x28, #192]"
]
},
"vblendpd ymm0, ymm1, ymm2, 0011b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vblendpd ymm0, ymm1, ymm2, 0100b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v2.d[0], v3.d[0]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vblendpd ymm0, ymm1, ymm2, 0101b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v16.16b, v17.16b",
"mov v16.d[0], v18.d[0]",
"mov v2.d[0], v3.d[0]",
"str q2, [x28, #192]"
]
},
"vblendpd ymm0, ymm1, ymm2, 0110b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v16.16b, v17.16b",
"mov v16.d[1], v18.d[1]",
"mov v2.d[0], v3.d[0]",
"str q2, [x28, #192]"
]
},
"vblendpd ymm0, ymm1, ymm2, 0111b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v2.d[0], v3.d[0]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vblendpd ymm0, ymm1, ymm2, 1000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v2.d[1], v3.d[1]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vblendpd ymm0, ymm1, ymm2, 1001b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v16.16b, v17.16b",
"mov v16.d[0], v18.d[0]",
"mov v2.d[1], v3.d[1]",
"str q2, [x28, #192]"
]
},
"vblendpd ymm0, ymm1, ymm2, 1010b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v16.16b, v17.16b",
"mov v16.d[1], v18.d[1]",
"mov v2.d[1], v3.d[1]",
"str q2, [x28, #192]"
]
},
"vblendpd ymm0, ymm1, ymm2, 1011b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v2.d[1], v3.d[1]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vblendpd ymm0, ymm1, ymm2, 1100b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vblendpd ymm0, ymm1, ymm2, 1101b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"mov v16.16b, v17.16b",
"mov v16.d[0], v18.d[0]",
"str q2, [x28, #192]"
]
},
"vblendpd ymm0, ymm1, ymm2, 1110b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"mov v16.16b, v17.16b",
"mov v16.d[1], v18.d[1]",
"str q2, [x28, #192]"
]
},
"vblendpd ymm0, ymm1, ymm2, 1111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vpblendw xmm0, xmm1, xmm2, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpblendw xmm0, xmm1, xmm2, 00000001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.h[0], v18.h[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendw xmm0, xmm1, xmm2, 11111111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vpblendw ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpblendw ymm0, ymm1, ymm2, 00000001b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"mov v16.16b, v17.16b",
"mov v16.h[0], v18.h[0]",
"mov v2.h[0], v3.h[0]",
"str q2, [x28, #192]"
]
},
"vpblendw ymm0, ymm1, ymm2, 11111111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vpalignr xmm0, xmm1, xmm2, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0f 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vpalignr xmm0, xmm1, xmm2, 1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0f 128-bit"
],
"ExpectedArm64ASM": [
"ext v16.16b, v18.16b, v17.16b, #1",
"stp xzr, xzr, [x28, #192]"
]
},
"vpalignr xmm0, xmm1, xmm2, 15": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0f 128-bit"
],
"ExpectedArm64ASM": [
"ext v16.16b, v18.16b, v17.16b, #15",
"stp xzr, xzr, [x28, #192]"
]
},
"vpalignr xmm0, xmm1, xmm2, 16": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0f 128-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpalignr xmm0, xmm1, xmm2, 17": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0f 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ext v16.16b, v17.16b, v2.16b, #1",
"stp xzr, xzr, [x28, #192]"
]
},
"vpalignr ymm0, ymm1, ymm2, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0f 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vpalignr ymm0, ymm1, ymm2, 1": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x0f 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"ext v16.16b, v18.16b, v17.16b, #1",
"ext v3.16b, v3.16b, v2.16b, #1",
"str q3, [x28, #192]"
]
},
"vpalignr ymm0, ymm1, ymm2, 15": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x0f 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"ext v16.16b, v18.16b, v17.16b, #15",
"ext v3.16b, v3.16b, v2.16b, #15",
"str q3, [x28, #192]"
]
},
"vpalignr ymm0, ymm1, ymm2, 16": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x0f 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vpalignr ymm0, ymm1, ymm2, 17": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x0f 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"movi v3.2d, #0x0",
"ext v16.16b, v17.16b, v3.16b, #1",
"ext v2.16b, v2.16b, v3.16b, #1",
"str q2, [x28, #192]"
]
},
"vpextrb rax, xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x14 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.b[0]"
]
},
"vpextrb rax, xmm0, 15": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x14 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.b[15]"
]
},
"vpextrw rax, xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x15 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.h[0]"
]
},
"vpextrw rax, xmm0, 7": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x15 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.h[7]"
]
},
"vpextrd rax, xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[0]"
]
},
"vpextrd rax, xmm0, 3": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[3]"
]
},
"vpextrb [rax], xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x14 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.b}[0], [x4]"
]
},
"vpextrb [rax], xmm0, 15": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x14 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.b}[15], [x4]"
]
},
"vpextrw [rax], xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x15 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.h}[0], [x4]"
]
},
"vpextrw [rax], xmm0, 7": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x15 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.h}[7], [x4]"
]
},
"vpextrd [rax], xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.s}[0], [x4]"
]
},
"vpextrd [rax], xmm0, 3": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.s}[3], [x4]"
]
},
"vextractps eax, xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x17 128-bit"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[0]"
]
},
"vextractps eax, xmm0, 3": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x17 128-bit"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[3]"
]
},
"vinsertf128 ymm0, ymm1, xmm2, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x18 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vinsertf128 ymm0, ymm1, xmm2, 1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x18 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vextractf128 xmm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x19 256-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vextractf128 xmm0, ymm1, 1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x19 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 6,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff3fffff",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
"msr fpcr, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x800000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
"msr fpcr, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x400000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
"msr fpcr, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 6,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"orr x0, x20, #0xc00000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
"msr fpcr, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"fcvtn v16.4h, v17.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 10,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff3fffff",
"msr fpcr, x0",
"fcvtn v3.4h, v17.4s",
"mov v0.16b, v3.16b",
"fcvtn2 v0.8h, v2.4s",
"mov v16.16b, v0.16b",
"msr fpcr, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, ymm1, 00000001b": {
"ExpectedInstructionCount": 11,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x800000",
"msr fpcr, x0",
"fcvtn v3.4h, v17.4s",
"mov v0.16b, v3.16b",
"fcvtn2 v0.8h, v2.4s",
"mov v16.16b, v0.16b",
"msr fpcr, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, ymm1, 00000010b": {
"ExpectedInstructionCount": 11,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x400000",
"msr fpcr, x0",
"fcvtn v3.4h, v17.4s",
"mov v0.16b, v3.16b",
"fcvtn2 v0.8h, v2.4s",
"mov v16.16b, v0.16b",
"msr fpcr, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, ymm1, 00000011b": {
"ExpectedInstructionCount": 10,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, fpcr",
"orr x0, x20, #0xc00000",
"msr fpcr, x0",
"fcvtn v3.4h, v17.4s",
"mov v0.16b, v3.16b",
"fcvtn2 v0.8h, v2.4s",
"mov v16.16b, v0.16b",
"msr fpcr, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vcvtps2ph xmm0, ymm1, 00000100b": {
"ExpectedInstructionCount": 6,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"fcvtn v3.4h, v17.4s",
"mov v0.16b, v3.16b",
"fcvtn2 v0.8h, v2.4s",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vpinsrb xmm0, xmm0, eax, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.b[0], w4",
"stp xzr, xzr, [x28, #192]"
]
},
"vpinsrb xmm0, xmm1, eax, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.b[0], w4",
"stp xzr, xzr, [x28, #192]"
]
},
"vpinsrb xmm0, xmm1, eax, 15": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.b[15], w4",
"stp xzr, xzr, [x28, #192]"
]
},
"vinsertps xmm0, xmm1, xmm2, ((0b00 << 6) | (0b00 << 4) | (0b0000))": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x21 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[0], v18.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vinsertps xmm0, xmm1, xmm2, ((0b00 << 6) | (0b00 << 4) | (0b1111))": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x21 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vinsertps xmm0, xmm1, xmm2, ((0b11 << 6) | (0b11 << 4) | (0b0000))": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x21 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[3], v18.s[3]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpinsrd xmm0, xmm0, eax, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.s[0], w4",
"stp xzr, xzr, [x28, #192]"
]
},
"vpinsrd xmm0, xmm1, eax, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[0], w4",
"stp xzr, xzr, [x28, #192]"
]
},
"vpinsrd xmm0, xmm1, eax, 3": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[3], w4",
"stp xzr, xzr, [x28, #192]"
]
},
"vpinsrq xmm0, xmm0, rax, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.d[0], x4",
"stp xzr, xzr, [x28, #192]"
]
},
"vpinsrq xmm0, xmm1, rax, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.d[0], x4",
"stp xzr, xzr, [x28, #192]"
]
},
"vpinsrq xmm0, xmm1, rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.d[1], x4",
"stp xzr, xzr, [x28, #192]"
]
},
"vinserti128 ymm0, ymm1, xmm2, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x38 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vinserti128 ymm0, ymm1, xmm2, 1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x38 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vextracti128 xmm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x39 256-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vextracti128 xmm0, ymm1, 1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x39 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"stp xzr, xzr, [x28, #192]"
]
},
"vdpps xmm0, xmm1, xmm2, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vdpps xmm0, xmm1, xmm2, 00001111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vdpps xmm0, xmm1, xmm2, 11110000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vdpps xmm0, xmm1, xmm2, 11111111b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"fmul v2.4s, v17.4s, v18.4s",
"faddp v2.4s, v2.4s, v2.4s",
"faddp s2, v2.2s",
"dup v16.4s, v2.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vdpps ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vdpps ymm0, ymm1, ymm2, 00001111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vdpps ymm0, ymm1, ymm2, 11110000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vdpps ymm0, ymm1, ymm2, 11111111b": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"fmul v4.4s, v17.4s, v18.4s",
"faddp v4.4s, v4.4s, v4.4s",
"faddp s4, v4.2s",
"dup v16.4s, v4.s[0]",
"fmul v2.4s, v2.4s, v3.4s",
"faddp v2.4s, v2.4s, v2.4s",
"faddp s2, v2.2s",
"dup v2.4s, v2.s[0]",
"str q2, [x28, #192]"
]
},
"vdppd xmm0, xmm1, xmm2, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x41 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vdppd xmm0, xmm1, xmm2, 00001111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x41 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vdppd xmm0, xmm1, xmm2, 11110000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x41 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vdppd xmm0, xmm1, xmm2, 11111111b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x41 128-bit"
],
"ExpectedArm64ASM": [
"fmul v2.2d, v17.2d, v18.2d",
"faddp d2, v2.2d",
"dup v16.2d, v2.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 000b": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[0]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h",
"stp xzr, xzr, [x28, #192]"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 001b": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[1]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h",
"stp xzr, xzr, [x28, #192]"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 010b": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[2]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h",
"stp xzr, xzr, [x28, #192]"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 011b": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[3]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h",
"stp xzr, xzr, [x28, #192]"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 100b": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[0]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h",
"stp xzr, xzr, [x28, #192]"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 101b": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[1]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h",
"stp xzr, xzr, [x28, #192]"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 110b": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[2]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h",
"stp xzr, xzr, [x28, #192]"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 111b": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[3]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h",
"stp xzr, xzr, [x28, #192]"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 000b": {
"ExpectedInstructionCount": 31,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v4.4s, v18.s[0]",
"ext v5.16b, v17.16b, v17.16b, #0",
"ext v6.16b, v17.16b, v17.16b, #1",
"ext v7.16b, v17.16b, v17.16b, #2",
"ext v8.16b, v17.16b, v17.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h",
"dup v3.4s, v3.s[0]",
"ext v4.16b, v2.16b, v2.16b, #0",
"ext v5.16b, v2.16b, v2.16b, #1",
"ext v6.16b, v2.16b, v2.16b, #2",
"ext v2.16b, v2.16b, v2.16b, #3",
"uabdl v4.8h, v4.8b, v3.8b",
"uabdl v5.8h, v5.8b, v3.8b",
"uabdl v6.8h, v6.8b, v3.8b",
"uabdl v2.8h, v2.8b, v3.8b",
"addp v3.8h, v4.8h, v6.8h",
"addp v2.8h, v5.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"str q2, [x28, #192]"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 001b": {
"ExpectedInstructionCount": 31,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v4.4s, v18.s[1]",
"ext v5.16b, v17.16b, v17.16b, #0",
"ext v6.16b, v17.16b, v17.16b, #1",
"ext v7.16b, v17.16b, v17.16b, #2",
"ext v8.16b, v17.16b, v17.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h",
"dup v3.4s, v3.s[0]",
"ext v4.16b, v2.16b, v2.16b, #0",
"ext v5.16b, v2.16b, v2.16b, #1",
"ext v6.16b, v2.16b, v2.16b, #2",
"ext v2.16b, v2.16b, v2.16b, #3",
"uabdl v4.8h, v4.8b, v3.8b",
"uabdl v5.8h, v5.8b, v3.8b",
"uabdl v6.8h, v6.8b, v3.8b",
"uabdl v2.8h, v2.8b, v3.8b",
"addp v3.8h, v4.8h, v6.8h",
"addp v2.8h, v5.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"str q2, [x28, #192]"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 010b": {
"ExpectedInstructionCount": 31,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v4.4s, v18.s[2]",
"ext v5.16b, v17.16b, v17.16b, #0",
"ext v6.16b, v17.16b, v17.16b, #1",
"ext v7.16b, v17.16b, v17.16b, #2",
"ext v8.16b, v17.16b, v17.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h",
"dup v3.4s, v3.s[0]",
"ext v4.16b, v2.16b, v2.16b, #0",
"ext v5.16b, v2.16b, v2.16b, #1",
"ext v6.16b, v2.16b, v2.16b, #2",
"ext v2.16b, v2.16b, v2.16b, #3",
"uabdl v4.8h, v4.8b, v3.8b",
"uabdl v5.8h, v5.8b, v3.8b",
"uabdl v6.8h, v6.8b, v3.8b",
"uabdl v2.8h, v2.8b, v3.8b",
"addp v3.8h, v4.8h, v6.8h",
"addp v2.8h, v5.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"str q2, [x28, #192]"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 011b": {
"ExpectedInstructionCount": 31,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v4.4s, v18.s[3]",
"ext v5.16b, v17.16b, v17.16b, #0",
"ext v6.16b, v17.16b, v17.16b, #1",
"ext v7.16b, v17.16b, v17.16b, #2",
"ext v8.16b, v17.16b, v17.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h",
"dup v3.4s, v3.s[0]",
"ext v4.16b, v2.16b, v2.16b, #0",
"ext v5.16b, v2.16b, v2.16b, #1",
"ext v6.16b, v2.16b, v2.16b, #2",
"ext v2.16b, v2.16b, v2.16b, #3",
"uabdl v4.8h, v4.8b, v3.8b",
"uabdl v5.8h, v5.8b, v3.8b",
"uabdl v6.8h, v6.8b, v3.8b",
"uabdl v2.8h, v2.8b, v3.8b",
"addp v3.8h, v4.8h, v6.8h",
"addp v2.8h, v5.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"str q2, [x28, #192]"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 100b": {
"ExpectedInstructionCount": 31,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v4.4s, v18.s[0]",
"ext v5.16b, v17.16b, v17.16b, #4",
"ext v6.16b, v17.16b, v17.16b, #5",
"ext v7.16b, v17.16b, v17.16b, #6",
"ext v8.16b, v17.16b, v17.16b, #7",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h",
"dup v3.4s, v3.s[0]",
"ext v4.16b, v2.16b, v2.16b, #0",
"ext v5.16b, v2.16b, v2.16b, #1",
"ext v6.16b, v2.16b, v2.16b, #2",
"ext v2.16b, v2.16b, v2.16b, #3",
"uabdl v4.8h, v4.8b, v3.8b",
"uabdl v5.8h, v5.8b, v3.8b",
"uabdl v6.8h, v6.8b, v3.8b",
"uabdl v2.8h, v2.8b, v3.8b",
"addp v3.8h, v4.8h, v6.8h",
"addp v2.8h, v5.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"str q2, [x28, #192]"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 101b": {
"ExpectedInstructionCount": 31,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v4.4s, v18.s[1]",
"ext v5.16b, v17.16b, v17.16b, #4",
"ext v6.16b, v17.16b, v17.16b, #5",
"ext v7.16b, v17.16b, v17.16b, #6",
"ext v8.16b, v17.16b, v17.16b, #7",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h",
"dup v3.4s, v3.s[0]",
"ext v4.16b, v2.16b, v2.16b, #0",
"ext v5.16b, v2.16b, v2.16b, #1",
"ext v6.16b, v2.16b, v2.16b, #2",
"ext v2.16b, v2.16b, v2.16b, #3",
"uabdl v4.8h, v4.8b, v3.8b",
"uabdl v5.8h, v5.8b, v3.8b",
"uabdl v6.8h, v6.8b, v3.8b",
"uabdl v2.8h, v2.8b, v3.8b",
"addp v3.8h, v4.8h, v6.8h",
"addp v2.8h, v5.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"str q2, [x28, #192]"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 110b": {
"ExpectedInstructionCount": 31,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v4.4s, v18.s[2]",
"ext v5.16b, v17.16b, v17.16b, #4",
"ext v6.16b, v17.16b, v17.16b, #5",
"ext v7.16b, v17.16b, v17.16b, #6",
"ext v8.16b, v17.16b, v17.16b, #7",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h",
"dup v3.4s, v3.s[0]",
"ext v4.16b, v2.16b, v2.16b, #0",
"ext v5.16b, v2.16b, v2.16b, #1",
"ext v6.16b, v2.16b, v2.16b, #2",
"ext v2.16b, v2.16b, v2.16b, #3",
"uabdl v4.8h, v4.8b, v3.8b",
"uabdl v5.8h, v5.8b, v3.8b",
"uabdl v6.8h, v6.8b, v3.8b",
"uabdl v2.8h, v2.8b, v3.8b",
"addp v3.8h, v4.8h, v6.8h",
"addp v2.8h, v5.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"str q2, [x28, #192]"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 111b": {
"ExpectedInstructionCount": 31,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v4.4s, v18.s[3]",
"ext v5.16b, v17.16b, v17.16b, #4",
"ext v6.16b, v17.16b, v17.16b, #5",
"ext v7.16b, v17.16b, v17.16b, #6",
"ext v8.16b, v17.16b, v17.16b, #7",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v4.8h, v8.8b, v4.8b",
"addp v5.8h, v5.8h, v7.8h",
"addp v4.8h, v6.8h, v4.8h",
"trn1 v6.4s, v5.4s, v4.4s",
"trn2 v4.4s, v5.4s, v4.4s",
"addp v16.8h, v6.8h, v4.8h",
"dup v3.4s, v3.s[0]",
"ext v4.16b, v2.16b, v2.16b, #0",
"ext v5.16b, v2.16b, v2.16b, #1",
"ext v6.16b, v2.16b, v2.16b, #2",
"ext v2.16b, v2.16b, v2.16b, #3",
"uabdl v4.8h, v4.8b, v3.8b",
"uabdl v5.8h, v5.8b, v3.8b",
"uabdl v6.8h, v6.8b, v3.8b",
"uabdl v2.8h, v2.8b, v3.8b",
"addp v3.8h, v4.8h, v6.8h",
"addp v2.8h, v5.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"str q2, [x28, #192]"
]
},
"vpclmulqdq xmm0, xmm1, xmm2, 00000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x44 128-bit"
],
"ExpectedArm64ASM": [
"pmull v16.1q, v17.1d, v18.1d",
"stp xzr, xzr, [x28, #192]"
]
},
"vpclmulqdq xmm0, xmm1, xmm2, 00001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x44 128-bit"
],
"ExpectedArm64ASM": [
"dup v0.2d, v17.d[1]",
"pmull v16.1q, v0.1d, v18.1d",
"stp xzr, xzr, [x28, #192]"
]
},
"vpclmulqdq xmm0, xmm1, xmm2, 10000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x44 128-bit"
],
"ExpectedArm64ASM": [
"dup v0.2d, v18.d[1]",
"pmull v16.1q, v0.1d, v17.1d",
"stp xzr, xzr, [x28, #192]"
]
},
"vpclmulqdq xmm0, xmm1, xmm2, 10001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x44 128-bit"
],
"ExpectedArm64ASM": [
"pmull2 v16.1q, v17.2d, v18.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vpclmulqdq ymm0, ymm1, ymm2, 00000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x44 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"pmull v16.1q, v17.1d, v18.1d",
"pmull v2.1q, v2.1d, v3.1d",
"str q2, [x28, #192]"
]
},
"vpclmulqdq ymm0, ymm1, ymm2, 00001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x44 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v0.2d, v17.d[1]",
"pmull v16.1q, v0.1d, v18.1d",
"dup v0.2d, v2.d[1]",
"pmull v2.1q, v0.1d, v3.1d",
"str q2, [x28, #192]"
]
},
"vpclmulqdq ymm0, ymm1, ymm2, 10000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x44 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"dup v0.2d, v18.d[1]",
"pmull v16.1q, v0.1d, v17.1d",
"dup v0.2d, v3.d[1]",
"pmull v2.1q, v0.1d, v2.1d",
"str q2, [x28, #192]"
]
},
"vpclmulqdq ymm0, ymm1, ymm2, 10001b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x44 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"pmull2 v16.1q, v17.2d, v18.2d",
"pmull2 v2.1q, v2.2d, v3.2d",
"str q2, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"str q17, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"str q17, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"str q17, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #224]",
"str q17, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"str q16, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010011b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q16, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"str q18, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #224]",
"str q18, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"str q2, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"ldr q2, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"str q2, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #224]",
"str q16, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00001000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"str q17, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00011000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"movi v16.2d, #0x0",
"str q2, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00101000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"str q18, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00111000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #224]",
"movi v16.2d, #0x0",
"str q2, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10001000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"stp xzr, xzr, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v17.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #208]",
"stp xzr, xzr, [x28, #192]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"stp xzr, xzr, [x28, #192]",
"mov v16.16b, v18.16b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vblendvps xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x4a 128-bit"
],
"ExpectedArm64ASM": [
"sshr v2.4s, v19.4s, #31",
"mov v16.16b, v2.16b",
"bsl v16.16b, v18.16b, v17.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vblendvps ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 3 0b01 0x4a 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"ldr q4, [x28, #240]",
"sshr v5.4s, v19.4s, #31",
"mov v16.16b, v5.16b",
"bsl v16.16b, v18.16b, v17.16b",
"sshr v4.4s, v4.4s, #31",
"bsl v4.16b, v3.16b, v2.16b",
"str q4, [x28, #192]"
]
},
"vblendvpd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x4b 128-bit"
],
"ExpectedArm64ASM": [
"sshr v2.2d, v19.2d, #63",
"mov v16.16b, v2.16b",
"bsl v16.16b, v18.16b, v17.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vblendvpd ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 3 0b01 0x4b 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"ldr q4, [x28, #240]",
"sshr v5.2d, v19.2d, #63",
"mov v16.16b, v5.16b",
"bsl v16.16b, v18.16b, v17.16b",
"sshr v4.2d, v4.2d, #63",
"bsl v4.16b, v3.16b, v2.16b",
"str q4, [x28, #192]"
]
},
"vpblendvb xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x4c 128-bit"
],
"ExpectedArm64ASM": [
"sshr v2.16b, v19.16b, #7",
"mov v16.16b, v2.16b",
"bsl v16.16b, v18.16b, v17.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vpblendvb ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 3 0b01 0x4c 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"ldr q4, [x28, #240]",
"sshr v5.16b, v19.16b, #7",
"mov v16.16b, v5.16b",
"bsl v16.16b, v18.16b, v17.16b",
"sshr v4.16b, v4.16b, #7",
"bsl v4.16b, v3.16b, v2.16b",
"str q4, [x28, #192]"
]
},
"vaeskeygenassist xmm0, xmm1, 0": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldr q3, [x28, #3312]",
"mov v16.16b, v17.16b",
"aese v16.16b, v2.16b",
"tbl v16.16b, {v16.16b}, v3.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vaeskeygenassist xmm0, xmm1, 0xFF": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldr q3, [x28, #3312]",
"mov v16.16b, v17.16b",
"aese v16.16b, v2.16b",
"tbl v16.16b, {v16.16b}, v3.16b",
"mov x0, #0xff00000000",
"dup v1.2d, x0",
"eor v16.16b, v16.16b, v1.16b",
"stp xzr, xzr, [x28, #192]"
]
}
}
}
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