mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 10:00:16 +02:00
454 lines
11 KiB
JSON
454 lines
11 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [
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"SVE128",
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"SVE256",
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"AFP"
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],
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"DisabledHostFeatures": [
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"RPRES"
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],
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"BinaryCacheVersion": 26
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},
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"Instructions": {
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"vsqrtss xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0x51 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fsqrt s16, s18"
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]
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},
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"vsqrtsd xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0x51 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fsqrt d16, d18"
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]
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},
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"vrsqrtss xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"FEAT_FPRES could make this more optimal",
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"Map 1 0b10 0x52 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fmov s0, #0x70 (1.0000)",
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"fsqrt s1, s18",
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"fdiv s0, s0, s1",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"vrcpss xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"FEAT_FPRES could make this more optimal",
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"Map 1 0b10 0x53 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fmov s0, #0x70 (1.0000)",
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"fdiv s0, s0, s18",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"vcmpss xmm0, xmm1, xmm2, 0x00": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmeq s16, s18, s17"
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]
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},
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"vcmpss xmm0, xmm1, xmm2, 0x01": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmgt s16, s18, s17"
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]
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},
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"vcmpss xmm0, xmm1, xmm2, 0x02": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmge s16, s18, s17"
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]
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},
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"vcmpss xmm0, xmm1, xmm2, 0x03": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"Map 1 0b10 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmge s0, s17, s18",
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"fcmgt s1, s18, s17",
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"orr v0.8b, v0.8b, v1.8b",
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"mvn v0.8b, v0.8b",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"vcmpss xmm0, xmm1, xmm2, 0x04": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b10 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmeq s0, s18, s17",
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"mvn v0.8b, v0.8b",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"vcmpss xmm0, xmm1, xmm2, 0x05": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b10 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt s2, s18, s17",
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"mvn v2.16b, v2.16b",
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"mov v16.16b, v17.16b",
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"mov v16.s[0], v2.s[0]"
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]
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},
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"vcmpss xmm0, xmm1, xmm2, 0x06": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b10 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"fcmge s2, s18, s17",
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"mvn v2.16b, v2.16b",
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"mov v16.16b, v17.16b",
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"mov v16.s[0], v2.s[0]"
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]
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},
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"vcmpss xmm0, xmm1, xmm2, 0x07": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b10 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmge s0, s17, s18",
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"fcmgt s1, s18, s17",
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"orr v0.8b, v0.8b, v1.8b",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"vcmpsd xmm0, xmm1, xmm2, 0x00": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmeq d16, d18, d17"
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]
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},
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"vcmpsd xmm0, xmm1, xmm2, 0x01": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmgt d16, d18, d17"
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]
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},
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"vcmpsd xmm0, xmm1, xmm2, 0x02": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmge d16, d18, d17"
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]
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},
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"vcmpsd xmm0, xmm1, xmm2, 0x03": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"Map 1 0b11 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmge d0, d17, d18",
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"fcmgt d1, d18, d17",
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"orr v0.8b, v0.8b, v1.8b",
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"mvn v0.8b, v0.8b",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"vcmpsd xmm0, xmm1, xmm2, 0x04": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b11 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmeq d0, d18, d17",
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"mvn v0.8b, v0.8b",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"vcmpsd xmm0, xmm1, xmm2, 0x05": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b11 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt d2, d18, d17",
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"mvn v2.16b, v2.16b",
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"mov v16.16b, v17.16b",
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"mov v16.d[0], v2.d[0]"
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]
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},
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"vcmpsd xmm0, xmm1, xmm2, 0x06": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b11 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"fcmge d2, d18, d17",
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"mvn v2.16b, v2.16b",
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"mov v16.16b, v17.16b",
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"mov v16.d[0], v2.d[0]"
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]
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},
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"vcmpsd xmm0, xmm1, xmm2, 0x07": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b11 0xC2 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcmge d0, d17, d18",
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"fcmgt d1, d18, d17",
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"orr v0.8b, v0.8b, v1.8b",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"vcvtsi2ss xmm0, xmm1, eax": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0x2A 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"scvtf s16, w4"
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]
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},
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"vcvtsi2ss xmm0, xmm1, rax": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0x2A 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"scvtf s16, x4"
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]
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},
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"vcvtsi2sd xmm0, xmm1, eax": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0x2A 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"scvtf d16, w4"
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]
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},
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"vcvtsi2sd xmm0, xmm1, rax": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0x2A 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"scvtf d16, x4"
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]
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},
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"vmulss xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0x59 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fmul s16, s17, s18"
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]
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},
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"vmulsd xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0x59 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fmul d16, d17, d18"
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]
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},
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"vcvtss2sd xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0x5a 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcvt d16, s18"
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]
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},
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"vcvtsd2ss xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0x5a 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fcvt s16, d18"
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]
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},
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"vsubss xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0x5c 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fsub s16, s17, s18"
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]
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},
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"vsubsd xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0x5c 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fsub d16, d17, d18"
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]
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},
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"vminss xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0x5d 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fmin s16, s17, s18"
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]
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},
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"vminsd xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0x5d 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fmin d16, d17, d18"
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]
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},
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"vdivss xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0x5e 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fdiv s16, s17, s18"
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]
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},
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"vdivsd xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0x5e 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fdiv d16, d17, d18"
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]
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},
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"vmaxss xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b10 0x5f 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fmax s16, s17, s18"
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]
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},
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"vmaxsd xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b11 0x5f 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b",
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"fmax d16, d17, d18"
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]
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},
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"vminps xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"Map 1 0b00 0x5d 128-bit"
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],
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"ExpectedArm64ASM": [
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"fmin v16.4s, v17.4s, v18.4s"
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]
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},
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"vminps ymm0, ymm1, ymm2": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0x5d 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt p0.s, p7/z, z18.s, z17.s",
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"not p0.b, p7/z, p0.b",
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"mov z0.d, z17.d",
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"mov z0.s, p0/m, z18.s",
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"mov z16.d, z0.d"
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]
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},
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"vminpd xmm0, xmm1, xmm2": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"Map 1 0b01 0x5d 128-bit"
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],
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"ExpectedArm64ASM": [
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"fmin v16.2d, v17.2d, v18.2d"
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]
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},
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"vminpd ymm0, ymm1, ymm2": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b01 0x5d 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt p0.d, p7/z, z18.d, z17.d",
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"not p0.b, p7/z, p0.b",
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"mov z0.d, z17.d",
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"mov z0.d, p0/m, z18.d",
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"mov z16.d, z0.d"
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]
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}
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}
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}
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