mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-08 02:00:16 +02:00
Ryan Houdek
5d37d5db1a
Need #3348 merged first. As I was casually thinking, this code made me realize that it was quite branch heavy and could likely be optimized to logic. The previous code generated some fairly nasty branch heavy code. This can be optimized to be branchless and take roughly five instructions per flag. Using a bitfield for each feature would turn each calculation in to 3-4 instructions but that seems overkill. Very minor thing.
266 lines
9.5 KiB
C++
266 lines
9.5 KiB
C++
// SPDX-License-Identifier: MIT
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#include "Interface/Core/CPUID.h"
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#include <FEXCore/Core/HostFeatures.h>
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#include "aarch64/assembler-aarch64.h"
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#include "aarch64/cpu-aarch64.h"
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#include "aarch64/disasm-aarch64.h"
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#include "aarch64/assembler-aarch64.h"
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#ifdef _M_X86_64
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#define XBYAK64
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#define XBYAK_CUSTOM_ALLOC
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#define XBYAK_CUSTOM_MALLOC FEXCore::Allocator::malloc
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#define XBYAK_CUSTOM_FREE FEXCore::Allocator::free
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#define XBYAK_CUSTOM_SETS
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#define XBYAK_STD_UNORDERED_SET fextl::unordered_set
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#define XBYAK_STD_UNORDERED_MAP fextl::unordered_map
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#define XBYAK_STD_UNORDERED_MULTIMAP fextl::unordered_multimap
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#define XBYAK_STD_LIST fextl::list
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#define XBYAK_NO_EXCEPTION
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#include <FEXCore/fextl/list.h>
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#include <FEXCore/fextl/unordered_map.h>
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#include <FEXCore/fextl/unordered_set.h>
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#include <xbyak/xbyak.h>
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#include <xbyak/xbyak_util.h>
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#endif
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namespace FEXCore {
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// Data Zero Prohibited flag
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// 0b0 = ZVA/GVA/GZVA permitted
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// 0b1 = ZVA/GVA/GZVA prohibited
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[[maybe_unused]] constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
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// Log2 of the blocksize in 32-bit words
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[[maybe_unused]] constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
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#ifdef _M_ARM_64
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[[maybe_unused]] static uint32_t GetDCZID() {
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uint64_t Result{};
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__asm("mrs %[Res], DCZID_EL0"
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: [Res] "=r" (Result));
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return Result;
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}
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static uint32_t GetFPCR() {
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uint64_t Result{};
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__asm ("mrs %[Res], FPCR"
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: [Res] "=r" (Result));
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return Result;
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}
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static void SetFPCR(uint64_t Value) {
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__asm ("msr FPCR, %[Value]"
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:: [Value] "r" (Value));
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}
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#else
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static uint32_t GetDCZID() {
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// Return unsupported
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return DCZID_DZP_MASK;
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}
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#endif
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static void OverrideFeatures(HostFeatures *Features) {
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// Override features if the user has specifically called for it.
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FEX_CONFIG_OPT(HostFeatures, HOSTFEATURES);
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if (!HostFeatures()) {
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// Early exit if no features are overriden.
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return;
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}
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#define ENABLE_DISABLE_OPTION(FeatureName, name, enum_name) \
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do { \
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const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
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const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0; \
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LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive"); \
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const bool AlreadyEnabled = Features->FeatureName; \
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const bool Result = (AlreadyEnabled | Enable##name) & !Disable##name; \
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Features->FeatureName = Result; \
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} while (0)
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#define GET_SINGLE_OPTION(name, enum_name) \
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const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
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const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0; \
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LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive");
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ENABLE_DISABLE_OPTION(SupportsAVX, AVX, AVX);
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ENABLE_DISABLE_OPTION(SupportsAVX2, AVX2, AVX2);
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ENABLE_DISABLE_OPTION(SupportsSVE, SVE, SVE);
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ENABLE_DISABLE_OPTION(SupportsAFP, AFP, AFP);
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ENABLE_DISABLE_OPTION(SupportsRCPC, LRCPC, LRCPC);
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ENABLE_DISABLE_OPTION(SupportsTSOImm9, LRCPC2, LRCPC2);
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ENABLE_DISABLE_OPTION(SupportsCSSC, CSSC, CSSC);
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ENABLE_DISABLE_OPTION(SupportsPMULL_128Bit, PMULL128, PMULL128);
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ENABLE_DISABLE_OPTION(SupportsRAND, RNG, RNG);
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ENABLE_DISABLE_OPTION(SupportsCLZERO, CLZERO, CLZERO);
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ENABLE_DISABLE_OPTION(SupportsAtomics, Atomics, ATOMICS);
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ENABLE_DISABLE_OPTION(SupportsFCMA, FCMA, FCMA);
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ENABLE_DISABLE_OPTION(SupportsFlagM, FlagM, FLAGM);
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ENABLE_DISABLE_OPTION(SupportsFlagM2, FlagM2, FLAGM2);
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ENABLE_DISABLE_OPTION(SupportsRPRES, RPRES, RPRES);
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GET_SINGLE_OPTION(Crypto, CRYPTO);
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#undef ENABLE_DISABLE_OPTION
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#undef GET_SINGLE_OPTION
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if (EnableCrypto) {
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Features->SupportsAES = true;
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Features->SupportsCRC = true;
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Features->SupportsSHA = true;
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Features->SupportsPMULL_128Bit = true;
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}
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else if (DisableCrypto) {
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Features->SupportsAES = false;
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Features->SupportsCRC = false;
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Features->SupportsSHA = false;
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Features->SupportsPMULL_128Bit = false;
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}
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}
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HostFeatures::HostFeatures() {
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#ifdef VIXL_SIMULATOR
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auto Features = vixl::CPUFeatures::All();
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// Vixl simulator doesn't support AFP.
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Features.Remove(vixl::CPUFeatures::Feature::kAFP);
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// Vixl simulator doesn't support RPRES.
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Features.Remove(vixl::CPUFeatures::Feature::kRPRES);
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#elif !defined(_WIN32)
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auto Features = vixl::CPUFeatures::InferFromOS();
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#else
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// Need to use ID registers in WINE.
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auto Features = vixl::CPUFeatures::InferFromIDRegisters();
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#endif
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SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
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SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
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SupportsSHA = Features.Has(vixl::CPUFeatures::Feature::kSHA1) &&
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Features.Has(vixl::CPUFeatures::Feature::kSHA2);
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SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
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SupportsRAND = Features.Has(vixl::CPUFeatures::Feature::kRNG);
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// Only supported when FEAT_AFP is supported
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SupportsAFP = Features.Has(vixl::CPUFeatures::Feature::kAFP);
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SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
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SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
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SupportsPMULL_128Bit = Features.Has(vixl::CPUFeatures::Feature::kPmull1Q);
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SupportsCSSC = Features.Has(vixl::CPUFeatures::Feature::kCSSC);
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SupportsFCMA = Features.Has(vixl::CPUFeatures::Feature::kFcma);
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SupportsFlagM = Features.Has(vixl::CPUFeatures::Feature::kFlagM);
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SupportsFlagM2 = Features.Has(vixl::CPUFeatures::Feature::kAXFlag);
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SupportsRPRES = Features.Has(vixl::CPUFeatures::Feature::kRPRES);
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Supports3DNow = true;
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SupportsSSE4A = true;
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#ifdef VIXL_SIMULATOR
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// Hardcode enable SVE with 256-bit wide registers.
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SupportsSVE = true;
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SupportsAVX = true;
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#else
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SupportsSVE = Features.Has(vixl::CPUFeatures::Feature::kSVE);
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SupportsAVX = Features.Has(vixl::CPUFeatures::Feature::kSVE2) &&
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vixl::aarch64::CPU::ReadSVEVectorLengthInBits() >= 256;
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#endif
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// TODO: AVX2 is currently unsupported. Disable until the remaining features are implemented.
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SupportsAVX2 = false;
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SupportsBMI1 = true;
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SupportsBMI2 = true;
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SupportsCLWB = true;
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// TODO: AFP is disabled until the scalar usage in the codebase can be audited to be working as expected.
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SupportsAFP = false;
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// RPRES has a dependency on AFP. Disable it until AFP is enabled.
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SupportsRPRES = false;
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if (!SupportsAtomics) {
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WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
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}
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#ifdef _M_ARM_64
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// We need to get the CPU's cache line size
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// We expect sane targets that have correct cacheline sizes across clusters
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uint64_t CTR;
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__asm volatile ("mrs %[ctr], ctr_el0"
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: [ctr] "=r"(CTR));
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DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
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ICacheLineSize = 4 << (CTR & 0xF);
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// Test if this CPU supports float exception trapping by attempting to enable
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// On unsupported these bits are architecturally defined as RAZ/WI
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constexpr uint32_t ExceptionEnableTraps =
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(1U << 8) | // Invalid Operation float exception trap enable
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(1U << 9) | // Divide by zero float exception trap enable
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(1U << 10) | // Overflow float exception trap enable
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(1U << 11) | // Underflow float exception trap enable
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(1U << 12) | // Inexact float exception trap enable
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(1U << 15); // Input Denormal float exception trap enable
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uint32_t OriginalFPCR = GetFPCR();
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uint32_t FPCR = OriginalFPCR | ExceptionEnableTraps;
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SetFPCR(FPCR);
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FPCR = GetFPCR();
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SupportsFloatExceptions = (FPCR & ExceptionEnableTraps) == ExceptionEnableTraps;
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// Set FPCR back to original just in case anything changed
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SetFPCR(OriginalFPCR);
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#endif
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#ifdef VIXL_SIMULATOR
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// simulator doesn't support dc(ZVA)
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SupportsCLZERO = false;
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// Simulator doesn't support SHA
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SupportsSHA = false;
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#else
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// Check if we can support cacheline clears
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uint32_t DCZID = GetDCZID();
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if ((DCZID & DCZID_DZP_MASK) == 0) {
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uint32_t DCZID_Log2 = DCZID & DCZID_BS_MASK;
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uint32_t DCZID_Bytes = (1 << DCZID_Log2) * sizeof(uint32_t);
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// If the DC ZVA size matches the emulated cache line size
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// This means we can use the instruction
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SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
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}
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#endif
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#if defined(_M_X86_64)
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// Hardcoded cacheline size.
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DCacheLineSize = 64U;
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ICacheLineSize = 64U;
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#if !defined(VIXL_SIMULATOR)
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Xbyak::util::Cpu X86Features{};
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SupportsAES = X86Features.has(Xbyak::util::Cpu::tAESNI);
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SupportsCRC = X86Features.has(Xbyak::util::Cpu::tSSE42);
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SupportsRAND = X86Features.has(Xbyak::util::Cpu::tRDRAND) && X86Features.has(Xbyak::util::Cpu::tRDSEED);
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SupportsRCPC = true;
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SupportsTSOImm9 = true;
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Supports3DNow = X86Features.has(Xbyak::util::Cpu::t3DN) && X86Features.has(Xbyak::util::Cpu::tE3DN);
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SupportsSSE4A = X86Features.has(Xbyak::util::Cpu::tSSE4a);
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SupportsAVX = true;
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SupportsAVX2 = true;
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SupportsSHA = X86Features.has(Xbyak::util::Cpu::tSHA);
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SupportsBMI1 = X86Features.has(Xbyak::util::Cpu::tBMI1);
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SupportsBMI2 = X86Features.has(Xbyak::util::Cpu::tBMI2);
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SupportsCLWB = X86Features.has(Xbyak::util::Cpu::tCLWB);
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SupportsPMULL_128Bit = X86Features.has(Xbyak::util::Cpu::tPCLMULQDQ);
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// xbyak doesn't know how to check for CLZero
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// First ensure we support a new enough extended CPUID function range
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uint32_t data[4];
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Xbyak::util::Cpu::getCpuid(0x8000'0000, data);
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if (data[0] >= 0x8000'0008U) {
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// CLZero defined in 8000_00008_EBX[bit 0]
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Xbyak::util::Cpu::getCpuid(0x8000'0008, data);
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SupportsCLZERO = data[1] & 1;
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}
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SupportsAFP = true;
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SupportsFloatExceptions = true;
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#endif
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#endif
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OverrideFeatures(this);
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}
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}
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