Alyssa Rosenzweig 5a3c0eb83c OpcodeDispatcher: fix shl with 8/16-bit variable ...

the special case here lines up with the special case of using a larger shift for
a smaller result, so we can just grab CF from the larger result.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-07-05 18:38:12 -04:00

..

Config

HostFeatures: Removes distinction between AVX and AVX2

2024-06-26 14:56:01 -07:00

Context

FEXCore: Implement support for fetching/setting YMM registers

2024-06-21 17:13:56 -04:00

Core

OpcodeDispatcher: fix shl with 8/16-bit variable

2024-07-05 18:38:12 -04:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

HLE/Thunks

IR: specify registers, not offsets for SRA

2024-05-08 14:01:42 -04:00

IR

RA: fix interaction between SRA & shuffles

2024-07-04 13:37:13 -04:00