mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-08 23:00:08 +02:00
Ryan Houdek
217bbf423b
Most constants don't need to be padded for relocations. So now that these have all been audited, switch to defaulting to NoPad to reduce verbosity. The number of constant that need to be explicitly padded are now marked and with all the prior changes, this allows bisecting if something has gone wrong.
518 lines
20 KiB
C++
518 lines
20 KiB
C++
// SPDX-License-Identifier: MIT
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#pragma once
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#include "CodeEmitter/Emitter.h"
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#include "Interface/IR/IR.h"
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#include "Interface/IR/IntrusiveIRList.h"
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#include <FEXCore/Core/CoreState.h>
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/fextl/vector.h>
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#include <algorithm>
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#include <stdint.h>
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#include <string.h>
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namespace FEXCore::IR {
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class IREmitter {
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public:
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IREmitter(FEXCore::Utils::IntrusivePooledAllocator& ThreadAllocator, bool SupportsTSOImm9)
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: DualListData {ThreadAllocator, 8 * 1024 * 1024}
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, SupportsTSOImm9(SupportsTSOImm9) {
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ReownOrClaimBuffer();
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ResetWorkingList();
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}
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virtual ~IREmitter() = default;
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void ReownOrClaimBuffer() {
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DualListData.ReownOrClaimBuffer();
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}
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void DelayedDisownBuffer() {
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DualListData.DelayedDisownBuffer();
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}
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IRListView ViewIR() {
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return IRListView(&DualListData);
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}
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void ResetWorkingList();
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/**
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* @name IR allocation routines
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*
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* @{ */
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RegClass WalkFindRegClass(Ref Node);
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// These inlining helpers are used by IRDefines.inc so define first.
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Ref InlineMem(OpSize Size, Ref Offset, MemOffsetType OffsetType, uint8_t& OffsetScale, bool TSO = false) {
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uint64_t Imm {};
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if (OffsetType != MemOffsetType::SXTX || !IsValueConstant(WrapNode(Offset), &Imm)) {
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return Offset;
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}
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// The immediate may be scaled in the IR, we need to correct for that.
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Imm *= OffsetScale;
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// Signed immediate unscaled 9-bit range for both regular and LRCPC2 ops.
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bool IsSIMM9 = ((int64_t)Imm >= -256) && ((int64_t)Imm <= 255);
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IsSIMM9 &= (SupportsTSOImm9 || !TSO);
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// Extended offsets for regular loadstore only.
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LOGMAN_THROW_A_FMT(Size >= IR::OpSize::i8Bit && Size <= IR::OpSize::i256Bit, "Must be sized");
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bool IsExtended = (Imm & (IR::OpSizeToSize(Size) - 1)) == 0 && Imm / IR::OpSizeToSize(Size) <= 4095;
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IsExtended &= !TSO;
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if (IsSIMM9 || IsExtended) {
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OffsetScale = 1;
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return _InlineConstant(Imm);
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} else {
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return Offset;
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}
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}
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#define DEF_INLINE(Type, Variable, Filter) \
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Ref Inline##Type(OpSize Size, Ref Source) { \
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uint64_t Variable; \
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if (IsValueConstant(WrapNode(Source), &Variable) && (Filter)) { \
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return _InlineConstant(Variable); \
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} else { \
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return Source; \
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} \
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}
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DEF_INLINE(Any, _, true)
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DEF_INLINE(Zero, X, X == 0)
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DEF_INLINE(AddSub, X, ARMEmitter::IsImmAddSub(X))
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DEF_INLINE(LargeAddSub, X, ARMEmitter::IsImmAddSub(X) && Size >= OpSize::i32Bit);
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DEF_INLINE(Logical, X, ARMEmitter::Emitter::IsImmLogical(X, std::max((int)IR::OpSizeAsBits(Size), 32)));
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Ref InlineSubtractZero(OpSize Size, Ref Src1, Ref Src2) {
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// Only inline a zero if we won't inline the other source.
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return IsValueConstant(WrapNode(Src2)) ? Src1 : InlineZero(Size, Src1);
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}
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#undef DEF_INLINE
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// These handlers add cost to the constructor and destructor
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// If it becomes an issue then blow them away
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// GCC also generates some pretty atrocious code around these
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// Use Clang!
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#define IROP_ALLOCATE_HELPERS
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#define IROP_DISPATCH_HELPERS
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#include <FEXCore/IR/IRDefines.inc>
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IRPair<IROp_Jump> _Jump() {
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return _Jump(InvalidNode);
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}
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IRPair<IROp_CondJump> _CondJump(Ref ssa0, CondClass cond = CondClass::NEQ) {
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return _CondJump(ssa0, _Constant(0), InvalidNode, InvalidNode, cond, GetOpSize(ssa0));
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}
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IRPair<IROp_CondJump> _CondJump(Ref ssa0, Ref ssa1, Ref ssa2, CondClass cond = CondClass::NEQ) {
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return _CondJump(ssa0, _Constant(0), ssa1, ssa2, cond, GetOpSize(ssa0));
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}
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IRPair<IROp_LoadContext> _LoadContextGPR(OpSize ByteSize, uint32_t Offset) {
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return _LoadContext(ByteSize, RegClass::GPR, Offset);
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}
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IRPair<IROp_LoadContext> _LoadContextFPR(OpSize ByteSize, uint32_t Offset) {
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return _LoadContext(ByteSize, RegClass::FPR, Offset);
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}
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IRPair<IROp_StoreContext> _StoreContextGPR(OpSize ByteSize, Ref Value, uint32_t Offset) {
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return _StoreContext(ByteSize, RegClass::GPR, Value, Offset);
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}
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IRPair<IROp_StoreContext> _StoreContextFPR(OpSize ByteSize, Ref Value, uint32_t Offset) {
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return _StoreContext(ByteSize, RegClass::FPR, Value, Offset);
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}
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IRPair<IROp_LoadContextIndexed> _LoadContextGPRIndexed(Ref Index, OpSize ByteSize, uint32_t BaseOffset, uint32_t Stride) {
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return _LoadContextIndexed(Index, ByteSize, BaseOffset, Stride, RegClass::GPR);
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}
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IRPair<IROp_LoadContextIndexed> _LoadContextFPRIndexed(Ref Index, OpSize ByteSize, uint32_t BaseOffset, uint32_t Stride) {
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return _LoadContextIndexed(Index, ByteSize, BaseOffset, Stride, RegClass::FPR);
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}
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IRPair<IROp_StoreContextIndexed> _StoreContextGPRIndexed(Ref Value, Ref Index, OpSize ByteSize, uint32_t BaseOffset, uint32_t Stride) {
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return _StoreContextIndexed(Value, Index, ByteSize, BaseOffset, Stride, RegClass::GPR);
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}
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IRPair<IROp_StoreContextIndexed> _StoreContextFPRIndexed(Ref Value, Ref Index, OpSize ByteSize, uint32_t BaseOffset, uint32_t Stride) {
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return _StoreContextIndexed(Value, Index, ByteSize, BaseOffset, Stride, RegClass::FPR);
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}
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IRPair<IROp_LoadMem> _LoadMem(RegClass Class, OpSize Size, Ref ssa0, OpSize Align = OpSize::i8Bit) {
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return _LoadMem(Class, Size, ssa0, Invalid(), Align, MemOffsetType::SXTX, 1);
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}
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IRPair<IROp_LoadMem> _LoadMemGPR(OpSize Size, Ref ssa0, OpSize Align = OpSize::i8Bit) {
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return _LoadMem(RegClass::GPR, Size, ssa0, Invalid(), Align, MemOffsetType::SXTX, 1);
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}
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IRPair<IROp_LoadMem> _LoadMemGPR(OpSize Size, Ref Addr, Ref Offset, OpSize Align, MemOffsetType OffsetType, uint8_t OffsetScale) {
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return _LoadMem(RegClass::GPR, Size, Addr, Offset, Align, OffsetType, OffsetScale);
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}
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IRPair<IROp_LoadMem> _LoadMemFPR(OpSize Size, Ref ssa0, OpSize Align = OpSize::i8Bit) {
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return _LoadMem(RegClass::FPR, Size, ssa0, Invalid(), Align, MemOffsetType::SXTX, 1);
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}
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IRPair<IROp_LoadMem> _LoadMemFPR(OpSize Size, Ref Addr, Ref Offset, OpSize Align, MemOffsetType OffsetType, uint8_t OffsetScale) {
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return _LoadMem(RegClass::FPR, Size, Addr, Offset, Align, OffsetType, OffsetScale);
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}
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IRPair<IROp_StoreMem> _StoreMem(RegClass Class, OpSize Size, Ref Addr, Ref Value, OpSize Align = OpSize::i8Bit) {
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return _StoreMem(Class, Size, Value, Addr, Invalid(), Align, MemOffsetType::SXTX, 1);
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}
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IRPair<IROp_StoreMem> _StoreMemGPR(OpSize Size, Ref Addr, Ref Value, OpSize Align = OpSize::i8Bit) {
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return _StoreMem(RegClass::GPR, Size, Value, Addr, Invalid(), Align, MemOffsetType::SXTX, 1);
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}
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IRPair<IROp_StoreMem> _StoreMemGPR(OpSize Size, Ref Value, Ref Addr, Ref Offset, OpSize Align, MemOffsetType OffsetType, uint8_t OffsetScale) {
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return _StoreMem(RegClass::GPR, Size, Value, Addr, Offset, Align, OffsetType, OffsetScale);
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}
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IRPair<IROp_StoreMem> _StoreMemFPR(OpSize Size, Ref Addr, Ref Value, OpSize Align = OpSize::i8Bit) {
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return _StoreMem(RegClass::FPR, Size, Value, Addr, Invalid(), Align, MemOffsetType::SXTX, 1);
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}
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IRPair<IROp_StoreMem> _StoreMemFPR(OpSize Size, Ref Value, Ref Addr, Ref Offset, OpSize Align, MemOffsetType OffsetType, uint8_t OffsetScale) {
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return _StoreMem(RegClass::FPR, Size, Value, Addr, Offset, Align, OffsetType, OffsetScale);
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}
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IRPair<IROp_StoreMemPair> _StoreMemPairGPR(OpSize Size, Ref Value1, Ref Value2, Ref Addr, uint32_t Offset) {
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return _StoreMemPair(RegClass::GPR, Size, Value1, Value2, Addr, Offset);
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}
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IRPair<IROp_StoreMemPair> _StoreMemPairFPR(OpSize Size, Ref Value1, Ref Value2, Ref Addr, uint32_t Offset) {
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return _StoreMemPair(RegClass::FPR, Size, Value1, Value2, Addr, Offset);
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}
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IRPair<IROp_Select> Select01(FEXCore::IR::OpSize CompareSize, CondClass Cond, OrderedNode* Cmp1, OrderedNode* Cmp2) {
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return _Select(OpSize::i64Bit, CompareSize, Cond, Cmp1, Cmp2, _InlineConstant(1), _InlineConstant(0));
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}
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IRPair<IROp_Select> To01(FEXCore::IR::OpSize CompareSize, OrderedNode* Cmp1) {
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return Select01(CompareSize, CondClass::NEQ, Cmp1, Constant(0));
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}
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IRPair<IROp_NZCVSelect> _NZCVSelect01(CondClass Cond) {
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return _NZCVSelect(OpSize::i64Bit, Cond, _InlineConstant(1), _InlineConstant(0));
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}
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Ref Addsub(IR::OpSize Size, IROps Op, IROps NegatedOp, Ref Src1, uint64_t Src2) {
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// Sign-extend the constant
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if (Size == OpSize::i32Bit) {
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Src2 = (int64_t)(int32_t)Src2;
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}
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// Negative constants need to be negated to inline.
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if (Src2 & (1ull << 63) && ARMEmitter::IsImmAddSub(-Src2)) {
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Op = NegatedOp;
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Src2 = -Src2;
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}
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auto Dest = _Add(Size, Src1, Constant(Src2));
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Dest.first->Header.Op = Op;
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return Dest;
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}
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Ref Add(IR::OpSize Size, Ref Src1, uint64_t Src2) {
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return Addsub(Size, OP_ADD, OP_SUB, Src1, Src2);
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}
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Ref Sub(IR::OpSize Size, Ref Src1, uint64_t Src2) {
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return Addsub(Size, OP_SUB, OP_ADD, Src1, Src2);
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}
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Ref AddWithFlags(IR::OpSize Size, Ref Src1, uint64_t Src2) {
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return Addsub(Size, OP_ADDWITHFLAGS, OP_SUBWITHFLAGS, Src1, Src2);
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}
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Ref SubWithFlags(IR::OpSize Size, Ref Src1, uint64_t Src2) {
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return Addsub(Size, OP_SUBWITHFLAGS, OP_ADDWITHFLAGS, Src1, Src2);
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}
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#define DEF_ADDSUB(Op) \
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Ref Op(IR::OpSize Size, Ref Src1, Ref Src2) { \
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uint64_t Constant; \
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if (IsValueConstant(WrapNode(Src2), &Constant)) { \
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return Op(Size, Src1, Constant); \
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} else { \
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return _##Op(Size, Src1, Src2); \
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} \
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}
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DEF_ADDSUB(Add)
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DEF_ADDSUB(Sub)
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DEF_ADDSUB(AddWithFlags)
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DEF_ADDSUB(SubWithFlags)
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struct ConstantData {
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int64_t Value;
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ConstPad Pad;
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int32_t MaxBytes;
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[[nodiscard]] auto operator<=>(const ConstantData&) const noexcept = default;
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};
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ConstantData Constants[32];
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Ref ConstantRefs[32];
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uint32_t NrConstants;
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Ref Constant(int64_t Value, ConstPad Pad = IR::ConstPad::NoPad, int32_t MaxBytes = 0) {
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const ConstantData Data {
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.Value = Value,
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.Pad = Pad,
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.MaxBytes = MaxBytes,
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};
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// Search for the constant in the pool.
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for (unsigned i = 0; i < std::min(NrConstants, 32u); ++i) {
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if (Constants[i] == Data) {
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return ConstantRefs[i];
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}
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}
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// Otherwise, materialize a fresh constant and pool it.
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Ref R = _Constant(Value, Pad, MaxBytes);
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unsigned i = (NrConstants++) & 31;
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Constants[i] = Data;
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ConstantRefs[i] = R;
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return R;
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}
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Ref Invalid() {
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return InvalidNode;
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}
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void SetJumpTarget(IR::IROp_Jump* Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting Jump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op->Header.Args[0].NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetTrueJumpTarget(IR::IROp_CondJump* Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting CondJump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op->TrueBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetFalseJumpTarget(IR::IROp_CondJump* Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting CondJump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op->FalseBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetJumpTarget(IRPair<IROp_Jump> Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting Jump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op.first->Header.Args[0].NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetTrueJumpTarget(IRPair<IROp_CondJump> Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting CondJump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op.first->TrueBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetFalseJumpTarget(IRPair<IROp_CondJump> Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting CondJump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op.first->FalseBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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/** @} */
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RegClass WalkFindRegClass(OrderedNodeWrapper ssa) {
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Ref RealNode = ssa.GetNode(DualListData.ListBegin());
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return WalkFindRegClass(RealNode);
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}
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bool IsValueConstant(OrderedNodeWrapper ssa, uint64_t* Constant = nullptr) {
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Ref RealNode = ssa.GetNode(DualListData.ListBegin());
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FEXCore::IR::IROp_Header* IROp = RealNode->Op(DualListData.DataBegin());
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if (IROp->Op == OP_CONSTANT) {
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auto Op = IROp->C<IR::IROp_Constant>();
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if (Constant) {
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*Constant = Op->Constant;
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}
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return true;
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}
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return false;
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}
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bool IsValueInlineConstant(OrderedNodeWrapper ssa) {
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Ref RealNode = ssa.GetNode(DualListData.ListBegin());
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FEXCore::IR::IROp_Header* IROp = RealNode->Op(DualListData.DataBegin());
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if (IROp->Op == OP_INLINECONSTANT) {
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return true;
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}
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return false;
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}
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FEXCore::IR::IROp_Header* GetOpHeader(OrderedNodeWrapper ssa) {
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Ref RealNode = ssa.GetNode(DualListData.ListBegin());
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return RealNode->Op(DualListData.DataBegin());
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}
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Ref UnwrapNode(OrderedNodeWrapper ssa) {
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return ssa.GetNode(DualListData.ListBegin());
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}
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OrderedNodeWrapper WrapNode(Ref node) {
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return node->Wrapped(DualListData.ListBegin());
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}
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NodeIterator GetIterator(OrderedNodeWrapper wrapper) {
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return NodeIterator(DualListData.ListBegin(), DualListData.DataBegin(), wrapper);
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}
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void ReplaceAllUsesWithRange(Ref Node, Ref NewNode, AllNodesIterator Begin, AllNodesIterator End);
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void ReplaceUsesWithAfter(Ref Node, Ref NewNode, AllNodesIterator After) {
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++After;
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ReplaceAllUsesWithRange(Node, NewNode, After, AllNodesIterator(DualListData.ListBegin(), DualListData.DataBegin()));
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}
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void ReplaceUsesWithAfter(Ref Node, Ref NewNode, Ref After) {
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auto Wrapped = After->Wrapped(DualListData.ListBegin());
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AllNodesIterator It = AllNodesIterator(DualListData.ListBegin(), DualListData.DataBegin(), Wrapped);
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ReplaceUsesWithAfter(Node, NewNode, It);
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}
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void ReplaceNodeArgument(Ref Node, uint8_t Arg, Ref NewArg);
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void Remove(Ref Node);
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void RemovePostRA(Ref Node);
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void CopyData(const IREmitter& rhs) {
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LOGMAN_THROW_A_FMT(rhs.DualListData.DataBackingSize() <= DualListData.DataBackingSize(), "Trying to take ownership of data that is too "
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"large");
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LOGMAN_THROW_A_FMT(rhs.DualListData.ListBackingSize() <= DualListData.ListBackingSize(), "Trying to take ownership of data that is too "
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"large");
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DualListData.CopyData(rhs.DualListData);
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InvalidNode = rhs.InvalidNode->Wrapped(rhs.DualListData.ListBegin()).GetNode(DualListData.ListBegin());
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CurrentWriteCursor = rhs.CurrentWriteCursor;
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CodeBlocks = rhs.CodeBlocks;
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for (auto& CodeBlock : CodeBlocks) {
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CodeBlock = CodeBlock->Wrapped(rhs.DualListData.ListBegin()).GetNode(DualListData.ListBegin());
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}
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}
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void SetWriteCursor(Ref Node) {
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CurrentWriteCursor = Node;
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}
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// Set cursor to write before Node
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void SetWriteCursorBefore(Ref Node) {
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auto IR = ViewIR();
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auto Before = IR.at(Node);
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--Before;
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SetWriteCursor((*Before).Node);
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}
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|
|
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Ref GetWriteCursor() {
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return CurrentWriteCursor;
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}
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|
|
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Ref GetCurrentBlock() {
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return CurrentCodeBlock;
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}
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|
|
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/**
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* @brief This creates an orphaned code node
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* The IROp backing is in the correct list but the OrderedNode lives outside of the list
|
|
*
|
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* XXX: This is because we don't want code blocks to interleave with current instruction IR ops currently
|
|
* We can change this behaviour once we remove the old BeginBlock/EndBlock types
|
|
*
|
|
* @return OrderedNode
|
|
*/
|
|
IRPair<IROp_CodeBlock> CreateCodeNode(bool EntryPoint = false, uint32_t GuestEntryOffset = 0) {
|
|
SetWriteCursor(nullptr); // Orphan from any previous nodes
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|
|
|
auto ID = ViewIR().GetHeader()->BlockCount++;
|
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auto CodeNode = _CodeBlock(InvalidNode, InvalidNode, ID, EntryPoint, GuestEntryOffset);
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|
|
|
CodeBlocks.emplace_back(CodeNode);
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|
|
|
SetWriteCursor(nullptr); // Orphan from any future nodes
|
|
|
|
auto Begin = _BeginBlock(CodeNode);
|
|
CodeNode.first->Begin = Begin.Node->Wrapped(DualListData.ListBegin());
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|
|
|
auto EndBlock = _EndBlock(CodeNode);
|
|
CodeNode.first->Last = EndBlock.Node->Wrapped(DualListData.ListBegin());
|
|
|
|
return CodeNode;
|
|
}
|
|
|
|
/**
|
|
* @name Links codeblocks together
|
|
* Codeblocks are singly linked so we need to walk the list forward if the linked block isn't isn't the last
|
|
*
|
|
* eq.
|
|
* CodeNode->Next -> Next
|
|
* to
|
|
* CodeNode->Next -> New -> Next
|
|
*
|
|
* @{ */
|
|
/** @} */
|
|
void LinkCodeBlocks(Ref CodeNode, Ref Next) {
|
|
[[maybe_unused]] auto CurrentIROp = CodeNode->Op(DualListData.DataBegin())->CW<FEXCore::IR::IROp_CodeBlock>();
|
|
#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
|
|
LOGMAN_THROW_A_FMT(CurrentIROp->Header.Op == IROps::OP_CODEBLOCK, "Invalid");
|
|
#endif
|
|
|
|
CodeNode->append(DualListData.ListBegin(), Next);
|
|
}
|
|
|
|
IRPair<IROp_CodeBlock> CreateNewCodeBlockAtEnd() {
|
|
return CreateNewCodeBlockAfter(nullptr);
|
|
}
|
|
IRPair<IROp_CodeBlock> CreateNewCodeBlockAfter(Ref insertAfter);
|
|
void SetCurrentCodeBlock(Ref Node);
|
|
|
|
protected:
|
|
void RemoveArgUses(Ref Node);
|
|
|
|
Ref CreateNode(IROp_Header* Op) {
|
|
uintptr_t ListBegin = DualListData.ListBegin();
|
|
size_t Size = sizeof(OrderedNode);
|
|
void* Ptr = DualListData.ListAllocate(Size);
|
|
Ref Node = new (Ptr) OrderedNode();
|
|
Node->Header.Value.SetOffset(DualListData.DataBegin(), reinterpret_cast<uintptr_t>(Op));
|
|
|
|
if (CurrentWriteCursor) {
|
|
CurrentWriteCursor->append(ListBegin, Node);
|
|
}
|
|
CurrentWriteCursor = Node;
|
|
return Node;
|
|
}
|
|
|
|
Ref GetNode(uint32_t SSANode) {
|
|
uintptr_t ListBegin = DualListData.ListBegin();
|
|
Ref Node = reinterpret_cast<Ref>(ListBegin + SSANode * sizeof(OrderedNode));
|
|
return Node;
|
|
}
|
|
|
|
Ref EmplaceOrphanedNode(Ref OldNode) {
|
|
size_t Size = sizeof(OrderedNode);
|
|
Ref Ptr = reinterpret_cast<Ref>(DualListData.ListAllocate(Size));
|
|
memcpy(Ptr, OldNode, Size);
|
|
return Ptr;
|
|
}
|
|
|
|
// MMX State can be either MMX (for 64bit) or x87 FPU (for 80bit)
|
|
enum { MMXState_MMX, MMXState_X87 } MMXState = MMXState_MMX;
|
|
|
|
// Overriden by dispatcher, stubbed for IR tests
|
|
virtual void RecordX87Use() {}
|
|
virtual void ChgStateX87_MMX() {}
|
|
virtual void ChgStateMMX_X87() {}
|
|
virtual void SaveNZCV(IROps Op) {}
|
|
|
|
Ref CurrentWriteCursor = nullptr;
|
|
|
|
// These could be combined with a little bit of work to be more efficient with memory usage. Isn't a big deal
|
|
DualIntrusiveAllocatorThreadPool DualListData;
|
|
|
|
Ref InvalidNode {};
|
|
Ref CurrentCodeBlock {};
|
|
fextl::vector<Ref> CodeBlocks;
|
|
uint64_t Entry {};
|
|
bool SupportsTSOImm9 {};
|
|
};
|
|
|
|
} // namespace FEXCore::IR
|