mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 09:00:17 +02:00
702 lines
17 KiB
JSON
702 lines
17 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"RPRES",
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"AFP",
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"FLAGM",
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"FLAGM2",
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"FRINTTS",
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"CSSC"
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],
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"BinaryCacheVersion": 19
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},
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"Instructions": {
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"movss xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf3 0x0f 0x10",
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"ExpectedArm64ASM": [
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"mov v16.s[0], v17.s[0]"
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]
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},
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"movss xmm0, [rax]": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf3 0x0f 0x10",
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"ExpectedArm64ASM": [
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"ldr s16, [x4]"
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]
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},
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"movss [rax], xmm0": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf3 0x0f 0x11",
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"ExpectedArm64ASM": [
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"str s16, [x4]"
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]
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},
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"movsldup xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf3 0x0f 0x12",
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"ExpectedArm64ASM": [
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"trn1 v16.4s, v17.4s, v17.4s"
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]
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},
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"movsldup xmm0, [rax]": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf3 0x0f 0x12",
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"ExpectedArm64ASM": [
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"ldr q2, [x4]",
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"trn1 v16.4s, v2.4s, v2.4s"
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]
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},
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"movshdup xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf3 0x0f 0x16",
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"ExpectedArm64ASM": [
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"trn2 v16.4s, v17.4s, v17.4s"
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]
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},
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"movshdup xmm0, [rax]": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf3 0x0f 0x16",
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"ExpectedArm64ASM": [
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"ldr q2, [x4]",
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"trn2 v16.4s, v2.4s, v2.4s"
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]
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},
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"cvtsi2ss xmm0, eax": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf3 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"scvtf s0, w4",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"cvtsi2ss xmm0, dword [rax]": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0xf3 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"ldr s2, [x4]",
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"scvtf s0, s2",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"cvtsi2ss xmm0, rax": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf3 0x0f 0x2a",
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"ExpectedArm64ASM": [
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"scvtf s0, x4",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"cvtsi2ss xmm0, qword [rax]": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0xf3 0x0f 0x2a"
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],
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"ExpectedArm64ASM": [
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"ldr x20, [x4]",
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"scvtf s0, x20",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"movntss [rax], xmm0": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf3 0x0f 0x2b",
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"ExpectedArm64ASM": [
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"str s16, [x4]"
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]
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},
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"cvttss2si eax, xmm0": {
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"ExpectedInstructionCount": 7,
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"Comment": "0xf3 0x0f 0x2c",
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"ExpectedArm64ASM": [
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"fcvtzs w20, s16",
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"mov w21, #0x80000000",
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"ldr s2, [x28, #3568]",
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"mrs x22, nzcv",
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"fcmp s2, s16",
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"csel w4, w20, w21, gt",
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"msr nzcv, x22"
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]
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},
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"cvttss2si eax, dword [rbx]": {
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"ExpectedInstructionCount": 8,
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"Comment": "0xf3 0x0f 0x2c",
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"ExpectedArm64ASM": [
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"ldr s2, [x6]",
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"fcvtzs w20, s2",
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"mov w21, #0x80000000",
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"ldr s3, [x28, #3568]",
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"mrs x22, nzcv",
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"fcmp s3, s2",
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"csel w4, w20, w21, gt",
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"msr nzcv, x22"
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]
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},
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"cvttss2si rax, xmm0": {
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"ExpectedInstructionCount": 7,
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"Comment": "0xf3 0x0f 0x2c",
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"ExpectedArm64ASM": [
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"fcvtzs x20, s16",
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"mov x21, #0x8000000000000000",
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"ldr s2, [x28, #3600]",
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"mrs x22, nzcv",
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"fcmp s2, s16",
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"csel x4, x20, x21, gt",
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"msr nzcv, x22"
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]
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},
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"cvttss2si rax, dword [rbx]": {
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"ExpectedInstructionCount": 8,
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"Comment": "0xf3 0x0f 0x2c",
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"ExpectedArm64ASM": [
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"ldr s2, [x6]",
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"fcvtzs x20, s2",
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"mov x21, #0x8000000000000000",
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"ldr s3, [x28, #3600]",
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"mrs x22, nzcv",
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"fcmp s3, s2",
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"csel x4, x20, x21, gt",
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"msr nzcv, x22"
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]
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},
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"cvtss2si eax, xmm0": {
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"ExpectedInstructionCount": 8,
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"Comment": "0xf3 0x0f 0x2d",
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"ExpectedArm64ASM": [
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"frinti s2, s16",
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"fcvtzs w20, s2",
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"mov w21, #0x80000000",
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"ldr s3, [x28, #3568]",
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"mrs x22, nzcv",
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"fcmp s3, s2",
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"csel w4, w20, w21, gt",
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"msr nzcv, x22"
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]
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},
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"cvtss2si eax, dword [rbx]": {
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"ExpectedInstructionCount": 9,
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"Comment": "0xf3 0x0f 0x2d",
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"ExpectedArm64ASM": [
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"ldr s2, [x6]",
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"frinti s2, s2",
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"fcvtzs w20, s2",
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"mov w21, #0x80000000",
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"ldr s3, [x28, #3568]",
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"mrs x22, nzcv",
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"fcmp s3, s2",
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"csel w4, w20, w21, gt",
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"msr nzcv, x22"
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]
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},
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"cvtss2si rax, xmm0": {
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"ExpectedInstructionCount": 8,
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"Comment": "0xf3 0x0f 0x2d",
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"ExpectedArm64ASM": [
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"frinti s2, s16",
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"fcvtzs x20, s2",
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"mov x21, #0x8000000000000000",
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"ldr s3, [x28, #3600]",
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"mrs x22, nzcv",
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"fcmp s3, s2",
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"csel x4, x20, x21, gt",
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"msr nzcv, x22"
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]
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},
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"cvtss2si rax, dword [rbx]": {
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"ExpectedInstructionCount": 9,
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"Comment": "0xf3 0x0f 0x2d",
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"ExpectedArm64ASM": [
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"ldr s2, [x6]",
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"frinti s2, s2",
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"fcvtzs x20, s2",
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"mov x21, #0x8000000000000000",
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"ldr s3, [x28, #3600]",
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"mrs x22, nzcv",
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"fcmp s3, s2",
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"csel x4, x20, x21, gt",
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"msr nzcv, x22"
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]
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},
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"sqrtss xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf3 0x0f 0x51",
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"ExpectedArm64ASM": [
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"fsqrt s0, s17",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"rsqrtss xmm0, xmm1": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"0xf3 0x0f 0x52"
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],
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"ExpectedArm64ASM": [
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"fmov s0, #0x70 (1.0000)",
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"fsqrt s1, s17",
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"fdiv s0, s0, s1",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"rcpss xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0xf3 0x0f 0x53"
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],
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"ExpectedArm64ASM": [
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"fmov s0, #0x70 (1.0000)",
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"fdiv s0, s0, s17",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"addss xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf3 0x0f 0x58"
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],
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"ExpectedArm64ASM": [
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"fadd s0, s16, s17",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"mulss xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf3 0x0f 0x59"
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],
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"ExpectedArm64ASM": [
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"fmul s0, s16, s17",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"cvtss2sd xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": "0xf3 0x0f 0x5a",
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"ExpectedArm64ASM": [
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"fcvt d0, s17",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cvtss2sd xmm0, [rax]": {
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"ExpectedInstructionCount": 3,
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"Comment": "0xf3 0x0f 0x5a",
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"ExpectedArm64ASM": [
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"ldr s2, [x4]",
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"fcvt d0, s2",
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"mov v16.d[0], v0.d[0]"
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]
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},
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"cvttps2dq xmm0, xmm1": {
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"ExpectedInstructionCount": 6,
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"Comment": "0xf3 0x0f 0x5b",
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #3664]",
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"ldr q3, [x28, #3568]",
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"fcvtzs v4.4s, v17.4s",
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"fcmgt v3.4s, v3.4s, v17.4s",
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"mov v16.16b, v3.16b",
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"bsl v16.16b, v4.16b, v2.16b"
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]
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},
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"subss xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf3 0x0f 0x5c"
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],
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"ExpectedArm64ASM": [
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"fsub s0, s16, s17",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"minss xmm0, xmm1": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"0xf3 0x0f 0x5d"
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],
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"ExpectedArm64ASM": [
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"mrs x20, nzcv",
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"fcmp s16, s17",
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"fcsel s0, s16, s17, mi",
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"mov v16.s[0], v0.s[0]",
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"msr nzcv, x20"
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]
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},
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"divss xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0xf3 0x0f 0x5e"
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],
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"ExpectedArm64ASM": [
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"fdiv s0, s16, s17",
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"mov v16.s[0], v0.s[0]"
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]
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},
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"maxss xmm0, xmm1": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"0xf3 0x0f 0x5f"
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],
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"ExpectedArm64ASM": [
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"mrs x20, nzcv",
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"fcmp s16, s17",
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"fcsel s0, s16, s17, gt",
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"mov v16.s[0], v0.s[0]",
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"msr nzcv, x20"
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]
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},
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"movdqu xmm0, xmm0": {
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"ExpectedInstructionCount": 0,
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"Comment": "0xf3 0x0f 0x6f",
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"ExpectedArm64ASM": []
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},
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"movdqu xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf3 0x0f 0x6f",
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b"
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]
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},
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"movdqu xmm0, [rax]": {
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"ExpectedInstructionCount": 1,
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"Comment": "0xf3 0x0f 0x6f",
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"ExpectedArm64ASM": [
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"ldr q16, [x4]"
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]
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},
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"pshufhw xmm0, xmm1, 0": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Broadcast upper-half element 0",
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"0xf3 0x0f 0x70"
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],
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"ExpectedArm64ASM": [
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"dup v2.8h, v17.h[4]",
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"trn1 v16.2d, v17.2d, v2.2d"
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]
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},
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"pshufhw xmm0, xmm1, 11100100b": {
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"ExpectedInstructionCount": 1,
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"Comment": [
|
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"Identity copy",
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"0xf3 0x0f 0x70"
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],
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"ExpectedArm64ASM": [
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"mov v16.16b, v17.16b"
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]
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},
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"pshufhw xmm0, xmm1, 01010000b": {
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"ExpectedInstructionCount": 3,
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"Comment": [
|
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"Upper elements Self-zip",
|
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"0xf3 0x0f 0x70"
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],
|
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"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2728]",
|
|
"ldr q2, [x0, #1280]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b"
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]
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},
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"pshufhw xmm0, xmm1, 1": {
|
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"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Broadcast element 0 in the upper-half",
|
|
"Upper-half Element 0 gets turned in to element 1",
|
|
"0xf3 0x0f 0x70"
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],
|
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"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2728]",
|
|
"ldr q2, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b"
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]
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},
|
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"pshufhw xmm0, xmm1, 0xff": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Broadcast upper-half Element 3",
|
|
"0xf3 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"dup v2.8h, v17.h[7]",
|
|
"trn1 v16.2d, v17.2d, v2.2d"
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|
]
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},
|
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"movq xmm0, xmm0": {
|
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"ExpectedInstructionCount": 1,
|
|
"Comment": "0xf3 0x0f 0x7e",
|
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"ExpectedArm64ASM": [
|
|
"mov v16.8b, v16.8b"
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]
|
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},
|
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"movq xmm0, xmm1": {
|
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"ExpectedInstructionCount": 1,
|
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"Comment": "0xf3 0x0f 0x7e",
|
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"ExpectedArm64ASM": [
|
|
"mov v16.8b, v17.8b"
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|
]
|
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},
|
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"movq xmm0, [rax]": {
|
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"ExpectedInstructionCount": 1,
|
|
"Comment": "0xf3 0x0f 0x7e",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d16, [x4]"
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|
]
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|
},
|
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"movdqu [rax], xmm0": {
|
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"ExpectedInstructionCount": 1,
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|
"Comment": "0xf3 0x0f 0x7f",
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
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]
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|
},
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"popcnt ax, bx": {
|
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"ExpectedInstructionCount": 9,
|
|
"Comment": "0xf3 0x0f 0xb8",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w6",
|
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"fmov s0, w20",
|
|
"cnt v0.8b, v0.8b",
|
|
"addp v0.8b, v0.8b, v0.8b",
|
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"umov w20, v0.b[0]",
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|
"bfxil x4, x20, #0, #16",
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|
"mov w27, #0x0",
|
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"cmp w20, #0x0 (0)",
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"mov w26, #0x1"
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]
|
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},
|
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"popcnt eax, ebx": {
|
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"ExpectedInstructionCount": 7,
|
|
"Comment": "0xf3 0x0f 0xb8",
|
|
"ExpectedArm64ASM": [
|
|
"fmov s0, w6",
|
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"cnt v0.8b, v0.8b",
|
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"addv b0, v0.8b",
|
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"umov w4, v0.b[0]",
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"mov w27, #0x0",
|
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"cmp w4, #0x0 (0)",
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"mov w26, #0x1"
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]
|
|
},
|
|
"popcnt rax, rbx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0xf3 0x0f 0xb8",
|
|
"ExpectedArm64ASM": [
|
|
"fmov d0, x6",
|
|
"cnt v0.8b, v0.8b",
|
|
"addv b0, v0.8b",
|
|
"umov w4, v0.b[0]",
|
|
"mov w27, #0x0",
|
|
"cmp w4, #0x0 (0)",
|
|
"mov w26, #0x1"
|
|
]
|
|
},
|
|
"tzcnt ax, bx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0xf3 0x0f 0xbc",
|
|
"ExpectedArm64ASM": [
|
|
"rbit w20, w6",
|
|
"orr w20, w20, #0x8000",
|
|
"clz w20, w20",
|
|
"bfxil x4, x20, #0, #16",
|
|
"cmn wzr, w20, lsl #16",
|
|
"eor x20, x20, #0x10",
|
|
"ubfx x20, x20, #4, #1",
|
|
"mrs x21, nzcv",
|
|
"bfi w21, w20, #29, #1",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"tzcnt eax, ebx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0xf3 0x0f 0xbc",
|
|
"ExpectedArm64ASM": [
|
|
"rbit w4, w6",
|
|
"clz w4, w4",
|
|
"cmp w4, #0x0 (0)",
|
|
"eor x20, x4, #0x20",
|
|
"ubfx x20, x20, #5, #1",
|
|
"mrs x21, nzcv",
|
|
"bfi w21, w20, #29, #1",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"tzcnt rax, rbx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0xf3 0x0f 0xbc",
|
|
"ExpectedArm64ASM": [
|
|
"rbit x4, x6",
|
|
"clz x4, x4",
|
|
"cmp x4, #0x0 (0)",
|
|
"eor x20, x4, #0x40",
|
|
"ubfx x20, x20, #6, #1",
|
|
"mrs x21, nzcv",
|
|
"bfi w21, w20, #29, #1",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"lzcnt ax, bx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0xf3 0x0f 0xbd",
|
|
"ExpectedArm64ASM": [
|
|
"lsl w20, w6, #16",
|
|
"orr w20, w20, #0x8000",
|
|
"clz w20, w20",
|
|
"bfxil x4, x20, #0, #16",
|
|
"cmn wzr, w20, lsl #16",
|
|
"eor x20, x20, #0x10",
|
|
"ubfx x20, x20, #4, #1",
|
|
"mrs x21, nzcv",
|
|
"bfi w21, w20, #29, #1",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"lzcnt eax, ebx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0xf3 0x0f 0xbd",
|
|
"ExpectedArm64ASM": [
|
|
"clz w4, w6",
|
|
"cmp w4, #0x0 (0)",
|
|
"eor x20, x4, #0x20",
|
|
"ubfx x20, x20, #5, #1",
|
|
"mrs x21, nzcv",
|
|
"bfi w21, w20, #29, #1",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"lzcnt rax, rbx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0xf3 0x0f 0xbd",
|
|
"ExpectedArm64ASM": [
|
|
"clz x4, x6",
|
|
"cmp x4, #0x0 (0)",
|
|
"eor x20, x4, #0x40",
|
|
"ubfx x20, x20, #6, #1",
|
|
"mrs x21, nzcv",
|
|
"bfi w21, w20, #29, #1",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"cmpss xmm0, xmm1, 0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0xf3 0x0f 0xc2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmeq s0, s17, s16",
|
|
"mov v16.s[0], v0.s[0]"
|
|
]
|
|
},
|
|
"cmpss xmm0, xmm1, 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0xf3 0x0f 0xc2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt s0, s17, s16",
|
|
"mov v16.s[0], v0.s[0]"
|
|
]
|
|
},
|
|
"cmpss xmm0, xmm1, 2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0xf3 0x0f 0xc2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge s0, s17, s16",
|
|
"mov v16.s[0], v0.s[0]"
|
|
]
|
|
},
|
|
"cmpss xmm0, xmm1, 3": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0xf3 0x0f 0xc2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge s0, s16, s17",
|
|
"fcmgt s1, s17, s16",
|
|
"orr v0.8b, v0.8b, v1.8b",
|
|
"mvn v0.8b, v0.8b",
|
|
"mov v16.s[0], v0.s[0]"
|
|
]
|
|
},
|
|
"cmpss xmm0, xmm1, 4": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0xf3 0x0f 0xc2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmeq s0, s17, s16",
|
|
"mvn v0.8b, v0.8b",
|
|
"mov v16.s[0], v0.s[0]"
|
|
]
|
|
},
|
|
"cmpss xmm0, xmm1, 5": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0xf3 0x0f 0xc2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt s2, s17, s16",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v16.s[0], v2.s[0]"
|
|
]
|
|
},
|
|
"cmpss xmm0, xmm1, 6": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0xf3 0x0f 0xc2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge s2, s17, s16",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v16.s[0], v2.s[0]"
|
|
]
|
|
},
|
|
"cmpss xmm0, xmm1, 7": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"0xf3 0x0f 0xc2"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge s0, s16, s17",
|
|
"fcmgt s1, s17, s16",
|
|
"orr v0.8b, v0.8b, v1.8b",
|
|
"mov v16.s[0], v0.s[0]"
|
|
]
|
|
},
|
|
"movq2dq xmm0, mm0": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0xf3 0x0f 0xd6",
|
|
"ExpectedArm64ASM": [
|
|
"strb wzr, [x28, #1051]",
|
|
"mov w20, #0xffff",
|
|
"strb w20, [x28, #1202]",
|
|
"ldr d16, [x28, #1056]"
|
|
]
|
|
},
|
|
"cvtdq2pd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0xf3 0x0f 0xe6",
|
|
"ExpectedArm64ASM": [
|
|
"sxtl v2.2d, v17.2s",
|
|
"scvtf v16.2d, v2.2d"
|
|
]
|
|
},
|
|
"cvtdq2pd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0xf3 0x0f 0xe6",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"sxtl v2.2d, v2.2s",
|
|
"scvtf v16.2d, v2.2d"
|
|
]
|
|
}
|
|
}
|
|
}
|