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FEX-Emu--FEX/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"RPRES",
"AFP"
],
"BinaryCacheVersion": 19
},
"Comment": [
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
],
"Instructions": {
"movzx rax, byte [ecx - 257]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x101 (257)",
"mov w20, w20",
"ldrb w4, [x20]"
]
},
"movzx rax, byte [ecx - 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x100 (256)",
"mov w20, w20",
"ldrb w4, [x20]"
]
},
"movzx rax, byte [ecx + 255]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0xff (255)",
"mov w20, w20",
"ldrb w4, [x20]"
]
},
"movzx rax, byte [ecx + 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x100 (256)",
"mov w20, w20",
"ldrb w4, [x20]"
]
},
"movzx rax, byte [ecx + 4095]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0xfff (4095)",
"mov w20, w20",
"ldrb w4, [x20]"
]
},
"movzx rax, byte [ecx + 4096]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x1000 (4096)",
"mov w20, w20",
"ldrb w4, [x20]"
]
},
"movzx rax, word [ecx - 257]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x101 (257)",
"mov w20, w20",
"ldrh w4, [x20]"
]
},
"movzx rax, word [ecx - 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x100 (256)",
"mov w20, w20",
"ldrh w4, [x20]"
]
},
"movzx rax, word [ecx + 255]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0xff (255)",
"mov w20, w20",
"ldrh w4, [x20]"
]
},
"movzx rax, word [ecx + 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x100 (256)",
"mov w20, w20",
"ldrh w4, [x20]"
]
},
"movzx rax, word [ecx + 8190]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x1ffe",
"add x20, x7, x20",
"mov w20, w20",
"ldrh w4, [x20]"
]
},
"movzx rax, word [ecx + 8191]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x1fff",
"add x20, x7, x20",
"mov w20, w20",
"ldrh w4, [x20]"
]
},
"movzx rax, word [ecx + 8192]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x2000 (8192)",
"mov w20, w20",
"ldrh w4, [x20]"
]
},
"mov eax, dword [ecx - 257]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x101 (257)",
"mov w20, w20",
"ldr w4, [x20]"
]
},
"mov eax, dword [ecx - 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr w4, [x20]"
]
},
"mov eax, dword [ecx + 255]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0xff (255)",
"mov w20, w20",
"ldr w4, [x20]"
]
},
"mov eax, dword [ecx + 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr w4, [x20]"
]
},
"mov eax, dword [ecx + 16380]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x3ffc",
"add x20, x7, x20",
"mov w20, w20",
"ldr w4, [x20]"
]
},
"mov eax, dword [ecx + 16381]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x3ffd",
"add x20, x7, x20",
"mov w20, w20",
"ldr w4, [x20]"
]
},
"mov eax, dword [ecx + 16382]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x3ffe",
"add x20, x7, x20",
"mov w20, w20",
"ldr w4, [x20]"
]
},
"mov eax, dword [ecx + 16383]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x3fff",
"add x20, x7, x20",
"mov w20, w20",
"ldr w4, [x20]"
]
},
"mov eax, dword [ecx + 16384]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x4000 (16384)",
"mov w20, w20",
"ldr w4, [x20]"
]
},
"mov rax, qword [ecx - 257]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x101 (257)",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx - 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 255]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0xff (255)",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 32760]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ff8",
"add x20, x7, x20",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 32761]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ff9",
"add x20, x7, x20",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 32762]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ffa",
"add x20, x7, x20",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 32763]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ffb",
"add x20, x7, x20",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 32764]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ffc",
"add x20, x7, x20",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 32765]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ffd",
"add x20, x7, x20",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 32766]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ffe",
"add x20, x7, x20",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 32767]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7fff",
"add x20, x7, x20",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"mov rax, qword [ecx + 32768]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x8000 (32768)",
"mov w20, w20",
"ldr x4, [x20]"
]
},
"movzx rax, byte [rcx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldrb w4, [x7, x20, sxtx]"
]
},
"movzx rax, byte [rcx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldurb w4, [x7, #-256]"
]
},
"movzx rax, byte [rcx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrb w4, [x7, #255]"
]
},
"movzx rax, byte [rcx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrb w4, [x7, #256]"
]
},
"movzx rax, byte [rcx + 4095]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrb w4, [x7, #4095]"
]
},
"movzx rax, byte [rcx + 4096]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x1000",
"ldrb w4, [x7, x20, sxtx]"
]
},
"movzx rax, word [rcx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldrh w4, [x7, x20, sxtx]"
]
},
"movzx rax, word [rcx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldurh w4, [x7, #-256]"
]
},
"movzx rax, word [rcx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldurh w4, [x7, #255]"
]
},
"movzx rax, word [rcx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrh w4, [x7, #256]"
]
},
"movzx rax, word [rcx + 8190]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrh w4, [x7, #8190]"
]
},
"movzx rax, word [rcx + 8191]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x1fff",
"ldrh w4, [x7, x20, sxtx]"
]
},
"movzx rax, word [rcx + 8192]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x2000",
"ldrh w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [rcx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldr w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [rcx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur w4, [x7, #-256]"
]
},
"mov eax, dword [rcx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur w4, [x7, #255]"
]
},
"mov eax, dword [rcx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr w4, [x7, #256]"
]
},
"mov eax, dword [rcx + 16380]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr w4, [x7, #16380]"
]
},
"mov eax, dword [rcx + 16381]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3ffd",
"ldr w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [rcx + 16382]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3ffe",
"ldr w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [rcx + 16383]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3fff",
"ldr w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [rcx + 16384]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x4000",
"ldr w4, [x7, x20, sxtx]"
]
},
"mov rax, qword [rcx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldr x4, [x7, x20, sxtx]"
]
},
"mov rax, qword [rcx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur x4, [x7, #-256]"
]
},
"mov rax, qword [rcx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur x4, [x7, #255]"
]
},
"mov rax, qword [rcx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr x4, [x7, #256]"
]
},
"mov rax, qword [rcx + 32760]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr x4, [x7, #32760]"
]
},
"mov rax, qword [rcx + 32761]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x7ff9",
"ldr x4, [x7, x20, sxtx]"
]
},
"mov rax, qword [rcx + 32762]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x7ffa",
"ldr x4, [x7, x20, sxtx]"
]
},
"mov rax, qword [rcx + 32763]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x7ffb",
"ldr x4, [x7, x20, sxtx]"
]
},
"mov rax, qword [rcx + 32764]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x7ffc",
"ldr x4, [x7, x20, sxtx]"
]
},
"mov rax, qword [rcx + 32765]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x7ffd",
"ldr x4, [x7, x20, sxtx]"
]
},
"mov rax, qword [rcx + 32766]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x7ffe",
"ldr x4, [x7, x20, sxtx]"
]
},
"mov rax, qword [rcx + 32767]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x7fff",
"ldr x4, [x7, x20, sxtx]"
]
},
"mov rax, qword [rcx + 32768]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x8000",
"ldr x4, [x7, x20, sxtx]"
]
},
"movss xmm0, [rcx + 16379]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3ffb",
"ldr s16, [x7, x20, sxtx]"
]
},
"movss xmm0, [rcx + 16380]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr s16, [x7, #16380]"
]
},
"movss xmm0, [rcx + 16381]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3ffd",
"ldr s16, [x7, x20, sxtx]"
]
},
"movss xmm0, [rcx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldr s16, [x7, x20, sxtx]"
]
},
"movss xmm0, [rcx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur s16, [x7, #-256]"
]
},
"movss xmm0, [rcx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur s16, [x7, #255]"
]
},
"movss xmm0, [rcx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr s16, [x7, #256]"
]
},
"movsd xmm0, [rcx + 32759]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x7ff7",
"ldr d16, [x7, x20, sxtx]"
]
},
"movsd xmm0, [rcx + 32760]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr d16, [x7, #32760]"
]
},
"movsd xmm0, [rcx + 32761]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x7ff9",
"ldr d16, [x7, x20, sxtx]"
]
},
"movsd xmm0, [rcx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldr d16, [x7, x20, sxtx]"
]
},
"movsd xmm0, [rcx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur d16, [x7, #-256]"
]
},
"movsd xmm0, [rcx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur d16, [x7, #255]"
]
},
"movsd xmm0, [rcx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr d16, [x7, #256]"
]
},
"movq xmm0, [rcx + 65519]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0xffef",
"ldr d16, [x7, x20, sxtx]"
]
},
"movq xmm0, [rcx + 65520]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0xfff0",
"ldr d16, [x7, x20, sxtx]"
]
},
"movq xmm0, [rcx + 65521]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0xfff1",
"ldr d16, [x7, x20, sxtx]"
]
},
"movq xmm0, [rcx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldr d16, [x7, x20, sxtx]"
]
},
"movq xmm0, [rcx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur d16, [x7, #-256]"
]
},
"movq xmm0, [rcx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur d16, [x7, #255]"
]
},
"movq xmm0, [rcx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr d16, [x7, #256]"
]
},
"movss xmm0, [ecx + 16379]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x3ffb",
"add x20, x7, x20",
"mov w20, w20",
"ldr s16, [x20]"
]
},
"movss xmm0, [ecx + 16380]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x3ffc",
"add x20, x7, x20",
"mov w20, w20",
"ldr s16, [x20]"
]
},
"movss xmm0, [ecx + 16381]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x3ffd",
"add x20, x7, x20",
"mov w20, w20",
"ldr s16, [x20]"
]
},
"movss xmm0, [ecx - 257]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x101 (257)",
"mov w20, w20",
"ldr s16, [x20]"
]
},
"movss xmm0, [ecx - 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr s16, [x20]"
]
},
"movss xmm0, [ecx + 255]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0xff (255)",
"mov w20, w20",
"ldr s16, [x20]"
]
},
"movss xmm0, [ecx + 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr s16, [x20]"
]
},
"movsd xmm0, [ecx + 32759]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ff7",
"add x20, x7, x20",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movsd xmm0, [ecx + 32760]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ff8",
"add x20, x7, x20",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movsd xmm0, [ecx + 32761]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0x7ff9",
"add x20, x7, x20",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movsd xmm0, [ecx - 257]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x101 (257)",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movsd xmm0, [ecx - 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movsd xmm0, [ecx + 255]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0xff (255)",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movsd xmm0, [ecx + 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movq xmm0, [ecx + 65519]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0xffef",
"add x20, x7, x20",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movq xmm0, [ecx + 65520]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0xfff0",
"add x20, x7, x20",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movq xmm0, [ecx + 65521]": {
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"mov w20, #0xfff1",
"add x20, x7, x20",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movq xmm0, [ecx - 257]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x101 (257)",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movq xmm0, [ecx - 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movq xmm0, [ecx + 255]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0xff (255)",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"movq xmm0, [ecx + 256]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x7, #0x100 (256)",
"mov w20, w20",
"ldr d16, [x20]"
]
},
"prefetch [rcx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"sub x20, x7, #0x101 (257)",
"prfm pldl1keep, [x20]"
]
},
"prefetch [rcx - 256]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"sub x20, x7, #0x100 (256)",
"prfm pldl1keep, [x20]"
]
},
"prefetch [rcx + 255]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x7, #0xff (255)",
"prfm pldl1keep, [x20]"
]
},
"prefetch [rcx + 256]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x7, #0x100 (256)",
"prfm pldl1keep, [x20]"
]
},
"prefetch [rcx + 32760]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"mov w20, #0x7ff8",
"add x20, x7, x20",
"prfm pldl1keep, [x20]"
]
},
"prefetch [rcx + 32761]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"mov w20, #0x7ff9",
"add x20, x7, x20",
"prfm pldl1keep, [x20]"
]
},
"prefetch [rax + rcx*1]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7",
"prfm pldl1keep, [x20]"
]
},
"prefetch [rax + rcx*2]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #1",
"prfm pldl1keep, [x20]"
]
},
"prefetch [rax + rcx*4]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #2",
"prfm pldl1keep, [x20]"
]
},
"prefetch [rax + rcx*8]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #3",
"prfm pldl1keep, [x20]"
]
},
"movzx ebx, byte [rax + rcx*1]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrb w6, [x4, x7, sxtx]"
]
},
"movzx ebx, byte [rax + rcx*2]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #1",
"ldrb w6, [x20]"
]
},
"movzx ebx, byte [rax + rcx*4]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #2",
"ldrb w6, [x20]"
]
},
"movzx ebx, byte [rax + rcx*8]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #3",
"ldrb w6, [x20]"
]
},
"movzx ebx, word [rax + rcx*1]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrh w6, [x4, x7, sxtx]"
]
},
"movzx ebx, word [rax + rcx*2]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrh w6, [x4, x7, sxtx #1]"
]
},
"movzx ebx, word [rax + rcx*4]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #2",
"ldrh w6, [x20]"
]
},
"movzx ebx, word [rax + rcx*8]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #3",
"ldrh w6, [x20]"
]
},
"mov ebx, [rax + rcx*1]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr w6, [x4, x7, sxtx]"
]
},
"mov ebx, [rax + rcx*2]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #1",
"ldr w6, [x20]"
]
},
"mov ebx, [rax + rcx*4]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr w6, [x4, x7, sxtx #2]"
]
},
"mov ebx, [rax + rcx*8]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #3",
"ldr w6, [x20]"
]
},
"mov rbx, [rax + rcx*1]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr x6, [x4, x7, sxtx]"
]
},
"mov rbx, [rax + rcx*2]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #1",
"ldr x6, [x20]"
]
},
"mov rbx, [rax + rcx*4]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add x20, x4, x7, lsl #2",
"ldr x6, [x20]"
]
},
"mov rbx, [rax + rcx*8]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr x6, [x4, x7, sxtx #3]"
]
},
"mov ebx, fs:0x14": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr x20, [x28, #1000]",
"ldr w6, [x20, #20]"
]
},
"mov rbx, gs:0x14": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr x20, [x28, #992]",
"ldur x6, [x20, #20]"
]
},
"Multiple segment registers": {
"x86Insts": [
"mov rax, gs:0x100",
"mov rbx, gs:0x14"
],
"x86InstructionCount": 2,
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"ldr x20, [x28, #992]",
"ldr x4, [x20, #256]",
"ldr x20, [x28, #992]",
"ldur x6, [x20, #20]"
]
},
"vmovdqu ymm7,yword [rsi+0x60]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldp q23, q2, [x10, #96]",
"str q2, [x28, #304]"
]
},
"vmovdqu ymm7,yword [rsi+0x120]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldp q23, q2, [x10, #288]",
"str q2, [x28, #304]"
]
},
"vmovdqu ymm7,yword [rsi-0x60]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldp q23, q2, [x10, #-96]",
"str q2, [x28, #304]"
]
},
"vmovdqu ymm7,yword [rsi-0x400]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldp q23, q2, [x10, #-1024]",
"str q2, [x28, #304]"
]
},
"vmovdqu ymm7,yword [rsi-0x420]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"sub x20, x10, #0x420 (1056)",
"ldp q23, q2, [x20]",
"str q2, [x28, #304]"
]
},
"vmovdqu ymm7,yword [rsi+0x3d0]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldp q23, q2, [x10, #976]",
"str q2, [x28, #304]"
]
},
"vmovdqu ymm7,yword [rsi+0x400]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"add x20, x10, #0x400 (1024)",
"ldp q23, q2, [x20]",
"str q2, [x28, #304]"
]
},
"vmovdqa yword [rcx+0x60],ymm1": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"stp q17, q2, [x7, #96]"
]
},
"vmovdqa yword [rcx+0x3d0],ymm1": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"stp q17, q2, [x7, #976]"
]
},
"vmovdqa yword [rcx-0x3d0],ymm1": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"stp q17, q2, [x7, #-976]"
]
},
"vmovdqa yword [rcx+rsi-0x3d0],ymm1": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"add x20, x7, x10",
"stp q17, q2, [x20, #-976]"
]
}
}
}
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