mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-14 07:00:43 +02:00
This is a validation pass that attempts to prove the output from the RA pass is valid. The current design should be able to prove that the RA result is internally consistent. That no-matter what control flow path you take thought the control flow graph, the physical registers and spill slots will always contain a single possible SSA value. It also checks that the SSA values in the IR actually line up with the SSA value in the physical register.