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FEX-Emu--FEX/unittests/InstructionCountCI/FlagM/Atomics.json
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Simon Scherer bce8b13366 InstcountCI: Update
2026-09-02 07:47:24 +02:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"FLAGM",
"FLAGM2"
],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"AFP"
],
"BinaryCacheVersion": 7
},
"Instructions": {
"lock add byte [rax], cl": {
"ExpectedInstructionCount": 6,
"Comment": "0x00",
"ExpectedArm64ASM": [
"ldaddalb w7, w20, [x4]",
"eor x27, x20, x7",
"lsl w0, w20, #24",
"cmn w0, w7, lsl #24",
"add w26, w20, w7",
"cfinv"
]
},
"lock add word [rax], cx": {
"ExpectedInstructionCount": 6,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddalh w7, w20, [x4]",
"eor x27, x20, x7",
"lsl w0, w20, #16",
"cmn w0, w7, lsl #16",
"add w26, w20, w7",
"cfinv"
]
},
"lock add dword [rax], ecx": {
"ExpectedInstructionCount": 4,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal w7, w20, [x4]",
"eor x27, x20, x7",
"adds w26, w20, w7",
"cfinv"
]
},
"lock or byte [rax], cl": {
"ExpectedInstructionCount": 4,
"Comment": "0x08",
"ExpectedArm64ASM": [
"ldsetalb w7, w20, [x4]",
"orr w26, w20, w7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"lock or word [rax], cx": {
"ExpectedInstructionCount": 4,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetalh w7, w20, [x4]",
"orr w26, w20, w7",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock or dword [rax], ecx": {
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetal w7, w20, [x4]",
"orr w20, w20, w7",
"subs w26, w20, #0x0 (0)"
]
},
"lock adc byte [rax], cl": {
"ExpectedInstructionCount": 15,
"Comment": "0x10",
"ExpectedArm64ASM": [
"cinc w20, w7, lo",
"ldaddalb w20, w20, [x4]",
"eor x27, x20, x7",
"uxtb x21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxtb w26, w23",
"cmp w26, w22",
"cset x22, hs",
"cmn wzr, w26, lsl #24",
"rmif x22, #63, #nzCv",
"eor w21, w20, w21",
"eor w20, w26, w20",
"bic w20, w20, w21",
"rmif x20, #7, #nzcV"
]
},
"lock adc word [rax], cx": {
"ExpectedInstructionCount": 15,
"Comment": "0x11",
"ExpectedArm64ASM": [
"cinc w20, w7, lo",
"ldaddalh w20, w20, [x4]",
"eor x27, x20, x7",
"uxth x21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxth w26, w23",
"cmp w26, w22",
"cset x22, hs",
"cmn wzr, w26, lsl #16",
"rmif x22, #63, #nzCv",
"eor w21, w20, w21",
"eor w20, w26, w20",
"bic w20, w20, w21",
"rmif x20, #15, #nzcV"
]
},
"lock adc dword [rax], ecx": {
"ExpectedInstructionCount": 6,
"Comment": "0x11",
"ExpectedArm64ASM": [
"cinc w20, w7, lo",
"ldaddal w20, w20, [x4]",
"eor x27, x20, x7",
"cfinv",
"adcs w26, w20, w7",
"cfinv"
]
},
"lock sbb byte [rax], cl": {
"ExpectedInstructionCount": 17,
"Comment": "0x18",
"ExpectedArm64ASM": [
"cinc w20, w7, lo",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"eor x27, x20, x7",
"uxtb w20, w20",
"uxtb x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxtb w26, w23",
"cmp w20, w22",
"cset x22, hs",
"cmn wzr, w26, lsl #24",
"rmif x22, #63, #nzCv",
"eor w21, w20, w21",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #7, #nzcV"
]
},
"lock sbb word [rax], cx": {
"ExpectedInstructionCount": 17,
"Comment": "0x19",
"ExpectedArm64ASM": [
"cinc w20, w7, lo",
"neg w1, w20",
"ldaddalh w1, w20, [x4]",
"eor x27, x20, x7",
"uxth w20, w20",
"uxth x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxth w26, w23",
"cmp w20, w22",
"cset x22, hs",
"cmn wzr, w26, lsl #16",
"rmif x22, #63, #nzCv",
"eor w21, w20, w21",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #15, #nzcV"
]
},
"lock sbb dword [rax], ecx": {
"ExpectedInstructionCount": 5,
"Comment": "0x19",
"ExpectedArm64ASM": [
"cinc w20, w7, lo",
"neg w1, w20",
"ldaddal w1, w20, [x4]",
"eor x27, x20, x7",
"sbcs w26, w20, w7"
]
},
"lock and byte [rax], cl": {
"ExpectedInstructionCount": 5,
"Comment": "0x20",
"ExpectedArm64ASM": [
"mvn w1, w7",
"ldclralb w1, w20, [x4]",
"and w26, w20, w7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"lock and word [rax], cx": {
"ExpectedInstructionCount": 5,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w7",
"ldclralh w1, w20, [x4]",
"and w26, w20, w7",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock and dword [rax], ecx": {
"ExpectedInstructionCount": 4,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w7",
"ldclral w1, w20, [x4]",
"ands w26, w20, w7",
"cfinv"
]
},
"lock sub byte [rax], cl": {
"ExpectedInstructionCount": 6,
"Comment": "0x28",
"ExpectedArm64ASM": [
"neg w1, w7",
"ldaddalb w1, w20, [x4]",
"eor x27, x20, x7",
"lsl w0, w20, #24",
"cmp w0, w7, lsl #24",
"sub w26, w20, w7"
]
},
"lock sub word [rax], cx": {
"ExpectedInstructionCount": 6,
"Comment": "0x28",
"ExpectedArm64ASM": [
"neg w1, w7",
"ldaddalh w1, w20, [x4]",
"eor x27, x20, x7",
"lsl w0, w20, #16",
"cmp w0, w7, lsl #16",
"sub w26, w20, w7"
]
},
"lock sub dword [rax], ecx": {
"ExpectedInstructionCount": 4,
"Comment": "0x29",
"ExpectedArm64ASM": [
"neg w1, w7",
"ldaddal w1, w20, [x4]",
"eor x27, x20, x7",
"subs w26, w20, w7"
]
},
"lock xor byte [rax], cl": {
"ExpectedInstructionCount": 4,
"Comment": "0x30",
"ExpectedArm64ASM": [
"ldeoralb w7, w20, [x4]",
"eor w26, w20, w7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"lock xor word [rax], cx": {
"ExpectedInstructionCount": 4,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoralh w7, w20, [x4]",
"eor w26, w20, w7",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock xor dword [rax], ecx": {
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoral w7, w20, [x4]",
"eor w20, w20, w7",
"subs w26, w20, #0x0 (0)"
]
},
"lock add qword [rax], rcx": {
"ExpectedInstructionCount": 4,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal x7, x20, [x4]",
"eor x27, x20, x7",
"adds x26, x20, x7",
"cfinv"
]
},
"xadd byte [rax], bl": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w6",
"ldaddalb w20, w21, [x4]",
"eor x27, x21, x20",
"lsl w0, w21, #24",
"cmn w0, w20, lsl #24",
"add w26, w21, w20",
"bfxil x6, x21, #0, #8",
"cfinv"
]
},
"xadd word [rax], bx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w6",
"ldaddalh w20, w21, [x4]",
"eor x27, x21, x20",
"lsl w0, w21, #16",
"cmn w0, w20, lsl #16",
"add w26, w21, w20",
"bfxil x6, x21, #0, #16",
"cfinv"
]
},
"xadd dword [rax], ebx": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w6",
"ldaddal w20, w6, [x4]",
"eor x27, x6, x20",
"adds w26, w6, w20",
"cfinv"
]
},
"xadd qword [rax], rbx": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"ldaddal x6, x20, [x4]",
"eor x27, x20, x6",
"adds x26, x20, x6",
"cfinv",
"mov x6, x20"
]
},
"lock add byte [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalb w20, w27, [x4]",
"lsl w0, w27, #24",
"cmn w0, w20, lsl #24",
"add w26, w27, #0x1 (1)",
"cfinv"
]
},
"lock add byte [rax], 0xFF": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldaddalb w20, w21, [x4]",
"mvn w27, w21",
"lsl w0, w21, #24",
"cmn w0, w20, lsl #24",
"add w26, w21, #0xff (255)",
"cfinv"
]
},
"lock add word [rax], 0x100": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldaddalh w20, w27, [x4]",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x100 (256)",
"cfinv"
]
},
"lock add word [rax], 0xFFFF": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldaddalh w20, w21, [x4]",
"mvn w27, w21",
"lsl w0, w21, #16",
"cmn w0, w20, lsl #16",
"add w26, w21, w20",
"cfinv"
]
},
"lock add dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldaddal w20, w27, [x4]",
"adds w26, w27, #0x100 (256)",
"cfinv"
]
},
"lock add dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldaddal w20, w20, [x4]",
"mvn w27, w20",
"subs w26, w20, #0x1 (1)",
"cfinv"
]
},
"lock add qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldaddal x20, x27, [x4]",
"adds x26, x27, #0x100 (256)",
"cfinv"
]
},
"lock add qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldaddal x20, x27, [x4]",
"adds x26, x27, x20",
"cfinv"
]
},
"lock add word [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalh w20, w27, [x4]",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x1 (1)",
"cfinv"
]
},
"lock add dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal w20, w27, [x4]",
"adds w26, w27, #0x1 (1)",
"cfinv"
]
},
"lock add qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal x20, x27, [x4]",
"adds x26, x27, #0x1 (1)",
"cfinv"
]
},
"lock or byte [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x80 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetalb w20, w20, [x4]",
"orr w26, w20, #0x1",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"lock or byte [rax], 0xFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x80 /1",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldsetalb w20, w20, [x4]",
"orr w26, w20, #0xff",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"lock or word [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetalh w20, w20, [x4]",
"orr w26, w20, #0x100",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock or word [rax], 0xFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldsetalh w20, w20, [x4]",
"orr w26, w20, #0xffff",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock or dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal w20, w20, [x4]",
"orr w20, w20, #0x100",
"subs w26, w20, #0x0 (0)"
]
},
"lock or dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldsetal w20, w21, [x4]",
"orr w20, w21, w20",
"subs w26, w20, #0x0 (0)"
]
},
"lock or qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal x20, x20, [x4]",
"orr x20, x20, #0x100",
"subs x26, x20, #0x0 (0)"
]
},
"lock or qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldsetal x20, x20, [x4]",
"orr x20, x20, #0xffffffff80000001",
"subs x26, x20, #0x0 (0)"
]
},
"lock or word [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetalh w20, w20, [x4]",
"orr w26, w20, #0x1",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock or dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal w20, w20, [x4]",
"orr w20, w20, #0x1",
"subs w26, w20, #0x0 (0)"
]
},
"lock or qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal x20, x20, [x4]",
"orr x20, x20, #0x1",
"subs x26, x20, #0x0 (0)"
]
},
"lock adc byte [rax], 1": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w21, w20, lo",
"ldaddalb w21, w27, [x4]",
"cinc w20, w20, lo",
"add w21, w27, w20",
"uxtb w26, w21",
"cmp w26, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV"
]
},
"lock adc byte [rax], 0xFF": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cinc w21, w20, lo",
"ldaddalb w21, w21, [x4]",
"mvn w27, w21",
"cinc w20, w20, lo",
"add w22, w21, w20",
"uxtb w26, w22",
"cmp w26, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w21, w26",
"rmif x20, #7, #nzcV"
]
},
"lock adc word [rax], 0x100": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc w21, w20, lo",
"ldaddalh w21, w27, [x4]",
"cinc w20, w20, lo",
"add w21, w27, w20",
"uxth w26, w21",
"cmp w26, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
]
},
"lock adc word [rax], 0xFFFF": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cinc w21, w20, lo",
"ldaddalh w21, w21, [x4]",
"mvn w27, w21",
"cinc w20, w20, lo",
"add w22, w21, w20",
"uxth w26, w22",
"cmp w26, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w21, w26",
"rmif x20, #15, #nzcV"
]
},
"lock adc dword [rax], 0x100": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc w21, w20, lo",
"ldaddal w21, w27, [x4]",
"cfinv",
"adcs w26, w27, w20",
"cfinv"
]
},
"lock adc dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cinc w21, w20, lo",
"ldaddal w21, w21, [x4]",
"mvn w27, w21",
"cfinv",
"adcs w26, w21, w20",
"cfinv"
]
},
"lock adc qword [rax], 0x100": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc x21, x20, lo",
"ldaddal x21, x27, [x4]",
"cfinv",
"adcs x26, x27, x20",
"cfinv"
]
},
"lock adc qword [rax], -2147483647": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"cinc x21, x20, lo",
"ldaddal x21, x27, [x4]",
"cfinv",
"adcs x26, x27, x20",
"cfinv"
]
},
"lock adc word [rax], 1": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w21, w20, lo",
"ldaddalh w21, w27, [x4]",
"cinc w20, w20, lo",
"add w21, w27, w20",
"uxth w26, w21",
"cmp w26, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
]
},
"lock adc dword [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w21, w20, lo",
"ldaddal w21, w27, [x4]",
"cfinv",
"adcs w26, w27, w20",
"cfinv"
]
},
"lock adc qword [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc x21, x20, lo",
"ldaddal x21, x27, [x4]",
"cfinv",
"adcs x26, x27, x20",
"cfinv"
]
},
"lock sbb byte [rax], 1": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalb w1, w27, [x4]",
"uxtb w21, w27",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w21, w26",
"rmif x20, #7, #nzcV"
]
},
"lock sbb byte [rax], 0xFF": {
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalb w1, w21, [x4]",
"mvn w27, w21",
"uxtb w21, w21",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w26, w21",
"rmif x20, #7, #nzcV"
]
},
"lock sbb word [rax], 0x100": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"uxth w21, w27",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w21, w26",
"rmif x20, #15, #nzcV"
]
},
"lock sbb word [rax], 0xFFFF": {
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalh w1, w21, [x4]",
"mvn w27, w21",
"uxth w21, w21",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w26, w21",
"rmif x20, #15, #nzcV"
]
},
"lock sbb dword [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"sbcs w26, w27, w20"
]
},
"lock sbb dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddal w1, w21, [x4]",
"mvn w27, w21",
"sbcs w26, w21, w20"
]
},
"lock sbb qword [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc x21, x20, lo",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sbcs x26, x27, x20"
]
},
"lock sbb qword [rax], -2147483647": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"cinc x21, x20, lo",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sbcs x26, x27, x20"
]
},
"lock sbb word [rax], 1": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"uxth w21, w27",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w21, w26",
"rmif x20, #15, #nzcV"
]
},
"lock sbb dword [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"sbcs w26, w27, w20"
]
},
"lock sbb qword [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc x21, x20, lo",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sbcs x26, x27, x20"
]
},
"lock and byte [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn w1, w20",
"ldclralb w1, w20, [x4]",
"and w26, w20, #0x1",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"lock and byte [rax], 0xFF": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /4",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w1, w20",
"ldclralb w1, w20, [x4]",
"and w26, w20, #0xff",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"lock and word [rax], 0x100": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mvn w1, w20",
"ldclralh w1, w20, [x4]",
"and w26, w20, #0x100",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock and word [rax], 0xFFFF": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"mvn w1, w20",
"ldclralh w1, w20, [x4]",
"and w26, w20, #0xffff",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock and dword [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mvn w1, w20",
"ldclral w1, w20, [x4]",
"ands w26, w20, #0x100",
"cfinv"
]
},
"lock and dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mvn w1, w20",
"ldclral w1, w21, [x4]",
"ands w26, w21, w20",
"cfinv"
]
},
"lock and qword [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mvn x1, x20",
"ldclral x1, x20, [x4]",
"ands x26, x20, #0x100",
"cfinv"
]
},
"lock and qword [rax], -2147483647": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"mvn x1, x20",
"ldclral x1, x20, [x4]",
"ands x26, x20, #0xffffffff80000001",
"cfinv"
]
},
"lock and word [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn w1, w20",
"ldclralh w1, w20, [x4]",
"and w26, w20, #0x1",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock and dword [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn w1, w20",
"ldclral w1, w20, [x4]",
"ands w26, w20, #0x1",
"cfinv"
]
},
"lock and qword [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn x1, x20",
"ldclral x1, x20, [x4]",
"ands x26, x20, #0x1",
"cfinv"
]
},
"lock sub byte [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"sub w26, w27, #0x1 (1)"
]
},
"lock sub byte [rax], 0xFF": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"neg w1, w20",
"ldaddalb w1, w21, [x4]",
"mvn w27, w21",
"lsl w0, w21, #24",
"cmp w0, w20, lsl #24",
"sub w26, w21, #0xff (255)"
]
},
"lock sub word [rax], 0x100": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"sub w26, w27, #0x100 (256)"
]
},
"lock sub word [rax], 0xFFFF": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"neg w1, w20",
"ldaddalh w1, w21, [x4]",
"mvn w27, w21",
"lsl w0, w21, #16",
"cmp w0, w20, lsl #16",
"sub w26, w21, w20"
]
},
"lock sub dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"neg w1, w20",
"ldaddal w1, w27, [x4]",
"subs w26, w27, #0x100 (256)"
]
},
"lock sub dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"neg w1, w20",
"ldaddal w1, w20, [x4]",
"mvn w27, w20",
"adds w26, w20, #0x1 (1)"
]
},
"lock sub qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"subs x26, x27, #0x100 (256)"
]
},
"lock sub qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"subs x26, x27, x20"
]
},
"lock sub word [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"sub w26, w27, #0x1 (1)"
]
},
"lock sub dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddal w1, w27, [x4]",
"subs w26, w27, #0x1 (1)"
]
},
"lock sub qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"subs x26, x27, #0x1 (1)"
]
},
"lock xor byte [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x80 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoralb w20, w20, [x4]",
"eor w26, w20, #0x1",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"lock xor byte [rax], 0xFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x80 /6",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldeoralb w20, w20, [x4]",
"eor w26, w20, #0xff",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"lock xor word [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoralh w20, w20, [x4]",
"eor w26, w20, #0x100",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock xor word [rax], 0xFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldeoralh w20, w20, [x4]",
"eor w26, w20, #0xffff",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock xor dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral w20, w20, [x4]",
"eor w20, w20, #0x100",
"subs w26, w20, #0x0 (0)"
]
},
"lock xor dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w21, [x4]",
"eor w20, w21, w20",
"subs w26, w20, #0x0 (0)"
]
},
"lock xor qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral x20, x20, [x4]",
"eor x20, x20, #0x100",
"subs x26, x20, #0x0 (0)"
]
},
"lock xor qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldeoral x20, x20, [x4]",
"eor x20, x20, #0xffffffff80000001",
"subs x26, x20, #0x0 (0)"
]
},
"lock xor word [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoralh w20, w20, [x4]",
"eor w26, w20, #0x1",
"cmn wzr, w26, lsl #16",
"cfinv"
]
},
"lock xor dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral w20, w20, [x4]",
"eor w20, w20, #0x1",
"subs w26, w20, #0x0 (0)"
]
},
"lock xor qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral x20, x20, [x4]",
"eor x20, x20, #0x1",
"subs x26, x20, #0x0 (0)"
]
},
"lock dec byte [rax]": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldaddalb w20, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"setf8 w26",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV"
]
},
"lock not byte [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldeoralb w20, w20, [x4]"
]
},
"lock not word [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldeoralh w20, w20, [x4]"
]
},
"lock not dword [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w20, [x4]"
]
},
"lock not qword [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ldeoral x20, x20, [x4]"
]
},
"lock neg byte [rax]": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"ldrb w1, [x4]",
"mov w3, w1",
"neg w2, w1",
"casalb w1, w2, [x4]",
"sub w2, w1, w3",
"cbnz w2, #-0x10",
"mov w27, w1",
"cmp wzr, w27, lsl #24",
"neg w26, w27"
]
},
"lock neg word [rax]": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldrh w1, [x4]",
"mov w3, w1",
"neg w2, w1",
"casalh w1, w2, [x4]",
"sub w2, w1, w3",
"cbnz w2, #-0x10",
"mov w27, w1",
"cmp wzr, w27, lsl #16",
"neg w26, w27"
]
},
"lock neg dword [rax]": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldr w1, [x4]",
"mov w3, w1",
"neg w2, w1",
"casal w1, w2, [x4]",
"sub w2, w1, w3",
"cbnz w2, #-0x10",
"mov w27, w1",
"negs w26, w27"
]
},
"lock neg qword [rax]": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldr x1, [x4]",
"mov x3, x1",
"neg x2, x1",
"casal x1, x2, [x4]",
"sub x2, x1, x3",
"cbnz x2, #-0x10",
"mov x27, x1",
"negs x26, x27"
]
},
"lock dec word [rax]": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldaddalh w20, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"setf16 w26",
"bic w20, w27, w26",
"rmif x20, #15, #nzcV"
]
},
"lock dec dword [rax]": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldaddal w20, w27, [x4]",
"cset x20, hs",
"subs w26, w27, #0x1 (1)",
"rmif x20, #63, #nzCv"
]
},
"lock dec qword [rax]": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ldaddal x20, x27, [x4]",
"cset x20, hs",
"subs x26, x27, #0x1 (1)",
"rmif x20, #63, #nzCv"
]
},
"lock inc byte [rax]": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalb w20, w27, [x4]",
"add w26, w27, #0x1 (1)",
"setf8 w26",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV"
]
},
"lock inc word [rax]": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalh w20, w27, [x4]",
"add w26, w27, #0x1 (1)",
"setf16 w26",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
]
},
"lock inc dword [rax]": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal w20, w27, [x4]",
"cset x20, hs",
"adds w26, w27, #0x1 (1)",
"rmif x20, #63, #nzCv"
]
},
"lock inc qword [rax]": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal x20, x27, [x4]",
"cset x20, hs",
"adds x26, x27, #0x1 (1)",
"rmif x20, #63, #nzCv"
]
},
"lock xadd byte [rcx], al": {
"ExpectedInstructionCount": 8,
"ExpectedArm64ASM": [
"uxtb w20, w4",
"ldaddalb w20, w21, [x7]",
"eor x27, x21, x20",
"lsl w0, w21, #24",
"cmn w0, w20, lsl #24",
"add w26, w21, w20",
"bfxil x4, x21, #0, #8",
"cfinv"
]
},
"lock xadd word [rcx], ax": {
"ExpectedInstructionCount": 8,
"ExpectedArm64ASM": [
"uxth w20, w4",
"ldaddalh w20, w21, [x7]",
"eor x27, x21, x20",
"lsl w0, w21, #16",
"cmn w0, w20, lsl #16",
"add w26, w21, w20",
"bfxil x4, x21, #0, #16",
"cfinv"
]
},
"lock xadd dword [rcx], eax": {
"ExpectedInstructionCount": 5,
"ExpectedArm64ASM": [
"mov w20, w4",
"ldaddal w20, w4, [x7]",
"eor x27, x4, x20",
"adds w26, w4, w20",
"cfinv"
]
},
"lock xadd qword [rcx], rax": {
"ExpectedInstructionCount": 5,
"ExpectedArm64ASM": [
"ldaddal x4, x20, [x7]",
"eor x27, x20, x4",
"adds x26, x20, x4",
"cfinv",
"mov x4, x20"
]
}
}
}
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