mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 08:00:15 +02:00
5398 lines
136 KiB
JSON
5398 lines
136 KiB
JSON
{
|
|
"Features": {
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|
"Bitness": 64,
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|
"EnabledHostFeatures": [
|
|
"FRINTTS"
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|
],
|
|
"DisabledHostFeatures": [
|
|
"FCMA",
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|
"RPRES",
|
|
"AFP",
|
|
"FLAGM",
|
|
"FLAGM2",
|
|
"SVE256",
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|
"SVE128"
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|
],
|
|
"BinaryCacheVersion": 7
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|
},
|
|
"Instructions": {
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|
"vmovups xmm0, xmm0": {
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|
"ExpectedInstructionCount": 1,
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|
"Comment": [
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|
"Map 1 0b00 0x10 128-bit"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
|
|
},
|
|
"vmovups xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
|
|
},
|
|
"vmovups ymm0, ymm0": {
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|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Spurious moves",
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|
"Map 1 0b00 0x10 256-bit"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"str q2, [x28, #192]"
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|
]
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|
},
|
|
"vmovups ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x10 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q16, q2, [x4]",
|
|
"str q2, [x28, #192]"
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|
]
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|
},
|
|
"vmovupd xmm0, xmm0": {
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|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
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|
"Map 1 0b01 0x10 128-bit"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
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|
},
|
|
"vmovupd xmm0, [rax]": {
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|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x10 128-bit"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
|
|
},
|
|
"vmovupd ymm0, ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Spurious moves",
|
|
"Map 1 0b01 0x10 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"str q2, [x28, #192]"
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|
]
|
|
},
|
|
"vmovupd ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x10 256-bit"
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|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q16, q2, [x4]",
|
|
"str q2, [x28, #192]"
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|
]
|
|
},
|
|
"vmovss xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b10 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
|
|
},
|
|
"vmovss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b10 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.s[0], v18.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
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|
},
|
|
"vmovsd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b11 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
|
|
},
|
|
"vmovsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b11 0x10 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.d[0], v18.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
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|
},
|
|
"vmovups [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b00 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"vmovups [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x11 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"stp q16, q2, [x4]"
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|
]
|
|
},
|
|
"vmovupd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
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|
]
|
|
},
|
|
"vmovupd [rax], ymm0": {
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|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x11 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"stp q16, q2, [x4]"
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|
]
|
|
},
|
|
"vmovss [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b10 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str s16, [x4]"
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|
]
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|
},
|
|
"db 0xc5, 0xf2, 0x11, 0xc2": {
|
|
"ExpectedInstructionCount": 3,
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|
"Comment": [
|
|
"vmovss xmm2, xmm1, xmm0",
|
|
"Need to manually encode since nasm won't encode this",
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|
"Map 1 0b10 0x11 128-bit"
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|
],
|
|
"ExpectedArm64ASM": [
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|
"mov v18.16b, v17.16b",
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|
"mov v18.s[0], v16.s[0]",
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|
"stp xzr, xzr, [x28, #224]"
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|
]
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},
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|
"vmovsd [rax], xmm0": {
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|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b11 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str d16, [x4]"
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|
]
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|
},
|
|
"db 0xc5, 0xf3, 0x11, 0xc2": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"vmovsd xmm2, xmm1, xmm0",
|
|
"Need to manually encode since nasm won't encode this",
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b11 0x11 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v18.16b, v17.16b",
|
|
"mov v18.d[0], v16.d[0]",
|
|
"stp xzr, xzr, [x28, #224]"
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|
]
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|
},
|
|
"vmovlps xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b00 0x12 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"ld1 {v16.d}[0], [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
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]
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},
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|
"vmovlpd xmm0, xmm1, [rax]": {
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|
"ExpectedInstructionCount": 3,
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|
"Comment": [
|
|
"Insert in to first element could be more optimal, which is the common case.",
|
|
"Map 1 0b01 0x12 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"ld1 {v16.d}[0], [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
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|
},
|
|
"vmovsldup xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b10 0x12 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"trn1 v16.4s, v2.4s, v2.4s",
|
|
"stp xzr, xzr, [x28, #192]"
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|
]
|
|
},
|
|
"vmovsldup ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x12 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q2, q3, [x4]",
|
|
"trn1 v16.4s, v2.4s, v2.4s",
|
|
"trn1 v2.4s, v3.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovddup xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b11 0x12 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"dup v16.2d, v2.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovddup ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x12 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q2, q3, [x4]",
|
|
"dup v16.2d, v2.d[0]",
|
|
"dup v2.2d, v3.d[0]",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovlps [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b00 0x13 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str d16, [x4]"
|
|
]
|
|
},
|
|
"vmovlpd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0x13 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str d16, [x4]"
|
|
]
|
|
},
|
|
"vunpcklps xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b00 0x14 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip1 v16.4s, v17.4s, v2.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vunpcklps ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x14 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldp q3, q4, [x4]",
|
|
"zip1 v16.4s, v17.4s, v3.4s",
|
|
"zip1 v2.4s, v2.4s, v4.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vunpcklpd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0x14 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip1 v16.2d, v17.2d, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vunpcklpd ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x14 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldp q3, q4, [x4]",
|
|
"zip1 v16.2d, v17.2d, v3.2d",
|
|
"zip1 v2.2d, v2.2d, v4.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vunpckhps xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b00 0x15 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip2 v16.4s, v17.4s, v2.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vunpckhps ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x15 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldp q3, q4, [x4]",
|
|
"zip2 v16.4s, v17.4s, v3.4s",
|
|
"zip2 v2.4s, v2.4s, v4.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vunpckhpd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0x15 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip2 v16.2d, v17.2d, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vunpckhpd ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x15 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldp q3, q4, [x4]",
|
|
"zip2 v16.2d, v17.2d, v3.2d",
|
|
"zip2 v2.2d, v2.2d, v4.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovhps xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b00 0x16 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"ld1 {v16.d}[1], [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovhpd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0x16 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"ld1 {v16.d}[1], [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovlhps xmm0, xmm1, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x16 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.2d, v17.2d, v17.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovshdup xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b10 0x16 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"trn2 v16.4s, v2.4s, v2.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovshdup ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x16 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q2, q3, [x4]",
|
|
"trn2 v16.4s, v2.4s, v2.4s",
|
|
"trn2 v2.4s, v3.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovhps [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b00 0x17 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.d}[1], [x4]"
|
|
]
|
|
},
|
|
"vmovhpd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0x17 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.d}[1], [x4]"
|
|
]
|
|
},
|
|
"vmovmskps rax, xmm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x50 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ushr v2.4s, v16.4s, #31",
|
|
"ldr q3, [x28, #3280]",
|
|
"ushl v2.4s, v2.4s, v3.4s",
|
|
"addv s2, v2.4s",
|
|
"mov w4, v2.s[0]"
|
|
]
|
|
},
|
|
"vmovmskps rax, ymm0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b00 0x50 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"uzp2 v2.8h, v16.8h, v2.8h",
|
|
"ushr v2.8h, v2.8h, #15",
|
|
"ldr q3, [x28, #3120]",
|
|
"ushl v2.8h, v2.8h, v3.8h",
|
|
"addv h2, v2.8h",
|
|
"umov w4, v2.h[0]"
|
|
]
|
|
},
|
|
"vmovmskpd rax, xmm0": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0x50 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uzp2 v2.4s, v16.4s, v16.4s",
|
|
"mov x20, v2.d[0]",
|
|
"bfi x20, x20, #31, #32",
|
|
"lsr x4, x20, #62"
|
|
]
|
|
},
|
|
"vmovmskpd rax, ymm0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b01 0x50 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"uzp2 v2.4s, v16.4s, v2.4s",
|
|
"ushr v2.4s, v2.4s, #31",
|
|
"ldr q3, [x28, #3280]",
|
|
"ushl v2.4s, v2.4s, v3.4s",
|
|
"addv s2, v2.4s",
|
|
"mov w4, v2.s[0]"
|
|
]
|
|
},
|
|
"vsqrtps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x51 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fsqrt v16.4s, v17.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vsqrtps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0x51 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"fsqrt v16.4s, v17.4s",
|
|
"fsqrt v2.4s, v2.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vsqrtpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x51 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fsqrt v16.2d, v17.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vsqrtpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0x51 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"fsqrt v16.2d, v17.2d",
|
|
"fsqrt v2.2d, v2.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vsqrtss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x51 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fsqrt s0, s18",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vsqrtsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x51 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fsqrt d0, d18",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vrsqrtps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0x52 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fsqrt v1.4s, v17.4s",
|
|
"fdiv v16.4s, v0.4s, v1.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vrsqrtps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"Map 1 0b00 0x52 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fsqrt v1.4s, v17.4s",
|
|
"fdiv v16.4s, v0.4s, v1.4s",
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fsqrt v1.4s, v2.4s",
|
|
"fdiv v2.4s, v0.4s, v1.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vrsqrtss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b10 0x52 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fmov s0, #0x70 (1.0000)",
|
|
"fsqrt s1, s18",
|
|
"fdiv s0, s0, s1",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vrcpps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b00 0x53 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fdiv v16.4s, v0.4s, v17.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vrcpps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b00 0x53 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fdiv v16.4s, v0.4s, v17.4s",
|
|
"fmov v0.4s, #0x70 (1.0000)",
|
|
"fdiv v2.4s, v0.4s, v2.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vrcpss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b10 0x53 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fmov s0, #0x70 (1.0000)",
|
|
"fdiv s0, s0, s18",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vandps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x54 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"and v16.16b, v16.16b, v17.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vandps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x54 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"and v16.16b, v16.16b, v17.16b",
|
|
"and v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vandpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x54 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"and v16.16b, v16.16b, v17.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vandpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x54 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"and v16.16b, v16.16b, v17.16b",
|
|
"and v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vandnps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x55 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"bic v16.16b, v17.16b, v16.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vandnps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x55 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"bic v16.16b, v17.16b, v16.16b",
|
|
"bic v2.16b, v3.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vandnpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x55 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"bic v16.16b, v17.16b, v16.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vandnpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x55 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"bic v16.16b, v17.16b, v16.16b",
|
|
"bic v2.16b, v3.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vorps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x56 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"orr v16.16b, v16.16b, v17.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vorps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x56 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"orr v16.16b, v16.16b, v17.16b",
|
|
"orr v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vorpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x56 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"orr v16.16b, v16.16b, v17.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vorpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x56 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"orr v16.16b, v16.16b, v17.16b",
|
|
"orr v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vxorps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x57 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor v16.16b, v16.16b, v17.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vxorps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x57 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"eor v16.16b, v16.16b, v17.16b",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vxorpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x57 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor v16.16b, v16.16b, v17.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vxorpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x57 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"eor v16.16b, v16.16b, v17.16b",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vxorps xmm0, xmm1, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"xor with itself to get zero register",
|
|
"Map 1 0b00 0x57 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v16.2d, #0x0",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vxorps ymm0, ymm1, ymm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"xor with itself to get zero register",
|
|
"Map 1 0b00 0x57 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v16.2d, #0x0",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vxorpd xmm0, xmm1, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"xor with itself to get zero register",
|
|
"Map 1 0b01 0x57 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v16.2d, #0x0",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vxorpd ymm0, ymm1, ymm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"xor with itself to get zero register",
|
|
"Map 1 0b01 0x57 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v16.2d, #0x0",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpcklbw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x60 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpcklbw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x60 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"zip1 v16.16b, v17.16b, v18.16b",
|
|
"zip1 v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpcklwd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x61 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpcklwd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x61 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"zip1 v16.8h, v17.8h, v18.8h",
|
|
"zip1 v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckldq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x62 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckldq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x62 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"zip1 v16.4s, v17.4s, v18.4s",
|
|
"zip1 v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpacksswb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0x63 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sqxtn v16.8b, v17.8h",
|
|
"sqxtn2 v16.16b, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpacksswb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b01 0x63 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sqxtn v16.8b, v17.8h",
|
|
"sqxtn2 v16.16b, v18.8h",
|
|
"sqxtn v2.8b, v2.8h",
|
|
"sqxtn2 v2.16b, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpgtb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x64 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cmgt v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpgtb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x64 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"cmgt v16.16b, v17.16b, v18.16b",
|
|
"cmgt v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpgtw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x65 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cmgt v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpgtw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x65 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"cmgt v16.8h, v17.8h, v18.8h",
|
|
"cmgt v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpgtd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x66 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cmgt v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpgtd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x66 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"cmgt v16.4s, v17.4s, v18.4s",
|
|
"cmgt v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpackuswb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0x67 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sqxtun v16.8b, v17.8h",
|
|
"sqxtun2 v16.16b, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpackuswb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b01 0x67 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sqxtun v16.8b, v17.8h",
|
|
"sqxtun2 v16.16b, v18.8h",
|
|
"sqxtun v2.8b, v2.8h",
|
|
"sqxtun2 v2.16b, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufd xmm0, xmm1, 00b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"dup v16.4s, v17.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufd xmm0, xmm1, 01b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2736]",
|
|
"ldr q2, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufd xmm0, xmm1, 10b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2736]",
|
|
"ldr q2, [x0, #32]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufd xmm0, xmm1, 11b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2736]",
|
|
"ldr q2, [x0, #48]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufd ymm0, ymm1, 00b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"dup v16.4s, v17.s[0]",
|
|
"dup v2.4s, v2.s[0]",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufd ymm0, ymm1, 01b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr x0, [x28, #2736]",
|
|
"ldr q3, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b}, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufd ymm0, ymm1, 10b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr x0, [x28, #2736]",
|
|
"ldr q3, [x0, #32]",
|
|
"tbl v16.16b, {v17.16b}, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufd ymm0, ymm1, 11b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr x0, [x28, #2736]",
|
|
"ldr q3, [x0, #48]",
|
|
"tbl v16.16b, {v17.16b}, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufhw xmm0, xmm1, 00b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"dup v2.8h, v17.h[4]",
|
|
"trn1 v16.2d, v17.2d, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufhw xmm0, xmm1, 01b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2728]",
|
|
"ldr q2, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufhw xmm0, xmm1, 10b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2728]",
|
|
"ldr q2, [x0, #32]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufhw xmm0, xmm1, 11b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2728]",
|
|
"ldr q2, [x0, #48]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufhw ymm0, ymm1, 00b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"dup v3.8h, v17.h[4]",
|
|
"trn1 v16.2d, v17.2d, v3.2d",
|
|
"dup v3.8h, v2.h[4]",
|
|
"trn1 v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufhw ymm0, ymm1, 01b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr x0, [x28, #2728]",
|
|
"ldr q3, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b}, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufhw ymm0, ymm1, 10b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr x0, [x28, #2728]",
|
|
"ldr q3, [x0, #32]",
|
|
"tbl v16.16b, {v17.16b}, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshufhw ymm0, ymm1, 11b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b10 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr x0, [x28, #2728]",
|
|
"ldr q3, [x0, #48]",
|
|
"tbl v16.16b, {v17.16b}, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshuflw xmm0, xmm1, 00b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"dup v2.8h, v17.h[0]",
|
|
"trn2 v16.2d, v2.2d, v17.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshuflw xmm0, xmm1, 01b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2720]",
|
|
"ldr q2, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshuflw xmm0, xmm1, 10b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2720]",
|
|
"ldr q2, [x0, #32]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshuflw xmm0, xmm1, 11b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2720]",
|
|
"ldr q2, [x0, #48]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshuflw ymm0, ymm1, 00b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"dup v3.8h, v17.h[0]",
|
|
"trn2 v16.2d, v3.2d, v17.2d",
|
|
"dup v3.8h, v2.h[0]",
|
|
"trn2 v2.2d, v3.2d, v2.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshuflw ymm0, ymm1, 01b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr x0, [x28, #2720]",
|
|
"ldr q3, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b}, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshuflw ymm0, ymm1, 10b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr x0, [x28, #2720]",
|
|
"ldr q3, [x0, #32]",
|
|
"tbl v16.16b, {v17.16b}, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpshuflw ymm0, ymm1, 11b": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b11 0x70 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr x0, [x28, #2720]",
|
|
"ldr q3, [x0, #48]",
|
|
"tbl v16.16b, {v17.16b}, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpeqb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x74 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cmeq v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpeqb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x74 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"cmeq v16.16b, v17.16b, v18.16b",
|
|
"cmeq v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpeqw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x75 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cmeq v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpeqw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x75 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"cmeq v16.8h, v17.8h, v18.8h",
|
|
"cmeq v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpeqd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x76 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cmeq v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpcmpeqd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x76 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"cmeq v16.4s, v17.4s, v18.4s",
|
|
"cmeq v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vzeroupper": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Might be able to use DZ ZVA",
|
|
"Map 1 0b01 0x77 L=0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v0.2d, #0x0",
|
|
"stp q0, q0, [x28, #192]",
|
|
"stp q0, q0, [x28, #224]",
|
|
"stp q0, q0, [x28, #256]",
|
|
"stp q0, q0, [x28, #288]",
|
|
"stp q0, q0, [x28, #320]",
|
|
"stp q0, q0, [x28, #352]",
|
|
"stp q0, q0, [x28, #384]",
|
|
"stp q0, q0, [x28, #416]"
|
|
]
|
|
},
|
|
"vzeroall": {
|
|
"ExpectedInstructionCount": 25,
|
|
"Comment": [
|
|
"Might be able to use DZ ZVA",
|
|
"Map 1 0b01 0x77 L=1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v16.2d, #0x0",
|
|
"movi v17.2d, #0x0",
|
|
"movi v18.2d, #0x0",
|
|
"movi v19.2d, #0x0",
|
|
"movi v20.2d, #0x0",
|
|
"movi v21.2d, #0x0",
|
|
"movi v22.2d, #0x0",
|
|
"movi v23.2d, #0x0",
|
|
"movi v24.2d, #0x0",
|
|
"movi v25.2d, #0x0",
|
|
"movi v26.2d, #0x0",
|
|
"movi v27.2d, #0x0",
|
|
"movi v28.2d, #0x0",
|
|
"movi v29.2d, #0x0",
|
|
"movi v30.2d, #0x0",
|
|
"movi v31.2d, #0x0",
|
|
"movi v0.2d, #0x0",
|
|
"stp q0, q0, [x28, #192]",
|
|
"stp q0, q0, [x28, #224]",
|
|
"stp q0, q0, [x28, #256]",
|
|
"stp q0, q0, [x28, #288]",
|
|
"stp q0, q0, [x28, #320]",
|
|
"stp q0, q0, [x28, #352]",
|
|
"stp q0, q0, [x28, #384]",
|
|
"stp q0, q0, [x28, #416]"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x00": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmeq v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x00": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmeq v16.4s, v17.4s, v18.4s",
|
|
"fcmeq v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x01": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v16.4s, v18.4s, v17.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x01": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmgt v16.4s, v18.4s, v17.4s",
|
|
"fcmgt v2.4s, v3.4s, v2.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x02": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v16.4s, v18.4s, v17.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x02": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmge v16.4s, v18.4s, v17.4s",
|
|
"fcmge v2.4s, v3.4s, v2.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x03": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v0.4s, v17.4s, v18.4s",
|
|
"fcmgt v1.4s, v18.4s, v17.4s",
|
|
"orr v16.16b, v0.16b, v1.16b",
|
|
"mvn v16.16b, v16.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x03": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmge v0.4s, v17.4s, v18.4s",
|
|
"fcmgt v1.4s, v18.4s, v17.4s",
|
|
"orr v16.16b, v0.16b, v1.16b",
|
|
"mvn v16.16b, v16.16b",
|
|
"fcmge v0.4s, v2.4s, v3.4s",
|
|
"fcmgt v1.4s, v3.4s, v2.4s",
|
|
"orr v2.16b, v0.16b, v1.16b",
|
|
"mvn v2.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x04": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmeq v16.4s, v17.4s, v18.4s",
|
|
"mvn v16.16b, v16.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x04": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmeq v16.4s, v17.4s, v18.4s",
|
|
"mvn v16.16b, v16.16b",
|
|
"fcmeq v2.4s, v2.4s, v3.4s",
|
|
"mvn v2.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x05": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v2.4s, v18.4s, v17.4s",
|
|
"mvn v16.16b, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x05": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmgt v4.4s, v18.4s, v17.4s",
|
|
"mvn v16.16b, v4.16b",
|
|
"fcmgt v2.4s, v3.4s, v2.4s",
|
|
"mvn v2.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x06": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v2.4s, v18.4s, v17.4s",
|
|
"mvn v16.16b, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x06": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmge v4.4s, v18.4s, v17.4s",
|
|
"mvn v16.16b, v4.16b",
|
|
"fcmge v2.4s, v3.4s, v2.4s",
|
|
"mvn v2.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps xmm0, xmm1, xmm2, 0x07": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v0.4s, v17.4s, v18.4s",
|
|
"fcmgt v1.4s, v18.4s, v17.4s",
|
|
"orr v16.16b, v0.16b, v1.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpps ymm0, ymm1, ymm2, 0x07": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmge v0.4s, v17.4s, v18.4s",
|
|
"fcmgt v1.4s, v18.4s, v17.4s",
|
|
"orr v16.16b, v0.16b, v1.16b",
|
|
"fcmge v0.4s, v2.4s, v3.4s",
|
|
"fcmgt v1.4s, v3.4s, v2.4s",
|
|
"orr v2.16b, v0.16b, v1.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x00": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmeq v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x00": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmeq v16.2d, v17.2d, v18.2d",
|
|
"fcmeq v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x01": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v16.2d, v18.2d, v17.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x01": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmgt v16.2d, v18.2d, v17.2d",
|
|
"fcmgt v2.2d, v3.2d, v2.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x02": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v16.2d, v18.2d, v17.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x02": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmge v16.2d, v18.2d, v17.2d",
|
|
"fcmge v2.2d, v3.2d, v2.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x03": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v0.2d, v17.2d, v18.2d",
|
|
"fcmgt v1.2d, v18.2d, v17.2d",
|
|
"orr v16.16b, v0.16b, v1.16b",
|
|
"mvn v16.16b, v16.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x03": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmge v0.2d, v17.2d, v18.2d",
|
|
"fcmgt v1.2d, v18.2d, v17.2d",
|
|
"orr v16.16b, v0.16b, v1.16b",
|
|
"mvn v16.16b, v16.16b",
|
|
"fcmge v0.2d, v2.2d, v3.2d",
|
|
"fcmgt v1.2d, v3.2d, v2.2d",
|
|
"orr v2.16b, v0.16b, v1.16b",
|
|
"mvn v2.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x04": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmeq v16.2d, v17.2d, v18.2d",
|
|
"mvn v16.16b, v16.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x04": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmeq v16.2d, v17.2d, v18.2d",
|
|
"mvn v16.16b, v16.16b",
|
|
"fcmeq v2.2d, v2.2d, v3.2d",
|
|
"mvn v2.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x05": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v2.2d, v18.2d, v17.2d",
|
|
"mvn v16.16b, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x05": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmgt v4.2d, v18.2d, v17.2d",
|
|
"mvn v16.16b, v4.16b",
|
|
"fcmgt v2.2d, v3.2d, v2.2d",
|
|
"mvn v2.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x06": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v2.2d, v18.2d, v17.2d",
|
|
"mvn v16.16b, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x06": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmge v4.2d, v18.2d, v17.2d",
|
|
"mvn v16.16b, v4.16b",
|
|
"fcmge v2.2d, v3.2d, v2.2d",
|
|
"mvn v2.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd xmm0, xmm1, xmm2, 0x07": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v0.2d, v17.2d, v18.2d",
|
|
"fcmgt v1.2d, v18.2d, v17.2d",
|
|
"orr v16.16b, v0.16b, v1.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmppd ymm0, ymm1, ymm2, 0x07": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmge v0.2d, v17.2d, v18.2d",
|
|
"fcmgt v1.2d, v18.2d, v17.2d",
|
|
"orr v16.16b, v0.16b, v1.16b",
|
|
"fcmge v0.2d, v2.2d, v3.2d",
|
|
"fcmgt v1.2d, v3.2d, v2.2d",
|
|
"orr v2.16b, v0.16b, v1.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x00": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmeq s0, s18, s17",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x01": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmgt s0, s18, s17",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x02": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmge s0, s18, s17",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x03": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmge s0, s17, s18",
|
|
"fcmgt s1, s18, s17",
|
|
"orr v0.8b, v0.8b, v1.8b",
|
|
"mvn v0.8b, v0.8b",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x04": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmeq s0, s18, s17",
|
|
"mvn v0.8b, v0.8b",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x05": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt s2, s18, s17",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.s[0], v2.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x06": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge s2, s18, s17",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.s[0], v2.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpss xmm0, xmm1, xmm2, 0x07": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b10 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmge s0, s17, s18",
|
|
"fcmgt s1, s18, s17",
|
|
"orr v0.8b, v0.8b, v1.8b",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x00": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmeq d0, d18, d17",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x01": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmgt d0, d18, d17",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x02": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmge d0, d18, d17",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x03": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmge d0, d17, d18",
|
|
"fcmgt d1, d18, d17",
|
|
"orr v0.8b, v0.8b, v1.8b",
|
|
"mvn v0.8b, v0.8b",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x04": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmeq d0, d18, d17",
|
|
"mvn v0.8b, v0.8b",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x05": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt d2, d18, d17",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.d[0], v2.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x06": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmge d2, d18, d17",
|
|
"mvn v2.16b, v2.16b",
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.d[0], v2.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcmpsd xmm0, xmm1, xmm2, 0x07": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b11 0xC2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcmge d0, d17, d18",
|
|
"fcmgt d1, d18, d17",
|
|
"orr v0.8b, v0.8b, v1.8b",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpinsrw xmm0, xmm0, eax, 000b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.h[0], w4",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpinsrw xmm0, xmm1, eax, 000b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.h[0], w4",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpinsrw xmm0, xmm1, eax, 001b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.h[1], w4",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpinsrw xmm0, xmm1, eax, 111b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.h[7], w4",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpextrw eax, xmm0, 000b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[0]"
|
|
]
|
|
},
|
|
"vpextrw eax, xmm0, 001b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[1]"
|
|
]
|
|
},
|
|
"vpextrw eax, xmm0, 111b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[7]"
|
|
]
|
|
},
|
|
"vpextrw [rax], xmm0, 000b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[0], [x4]"
|
|
]
|
|
},
|
|
"vpextrw [rax], xmm0, 001b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[1], [x4]"
|
|
]
|
|
},
|
|
"vpextrw [rax], xmm0, 111b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[7], [x4]"
|
|
]
|
|
},
|
|
"vshufps xmm0, xmm1, xmm2, 00b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"dup v2.4s, v17.s[0]",
|
|
"dup v3.4s, v18.s[0]",
|
|
"zip1 v16.2d, v2.2d, v3.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufps ymm0, ymm1, ymm2, 00b": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"dup v4.4s, v17.s[0]",
|
|
"dup v5.4s, v18.s[0]",
|
|
"zip1 v16.2d, v4.2d, v5.2d",
|
|
"dup v2.4s, v2.s[0]",
|
|
"dup v3.4s, v3.s[0]",
|
|
"zip1 v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufps xmm0, xmm1, xmm2, 01b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2744]",
|
|
"ldr q2, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufps ymm0, ymm1, ymm2, 01b": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"ldr x0, [x28, #2744]",
|
|
"ldr q4, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
|
|
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufps xmm0, xmm1, xmm2, 10b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2744]",
|
|
"ldr q2, [x0, #32]",
|
|
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufps ymm0, ymm1, ymm2, 10b": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"ldr x0, [x28, #2744]",
|
|
"ldr q4, [x0, #32]",
|
|
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
|
|
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufps xmm0, xmm1, xmm2, 11b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2744]",
|
|
"ldr q2, [x0, #48]",
|
|
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufps ymm0, ymm1, ymm2, 11b": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b00 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"ldr x0, [x28, #2744]",
|
|
"ldr q4, [x0, #48]",
|
|
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
|
|
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufpd xmm0, xmm1, xmm2, 0b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufpd ymm0, ymm1, ymm2, 0b": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"zip1 v16.2d, v17.2d, v18.2d",
|
|
"zip1 v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufpd xmm0, xmm1, xmm2, 1b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ext v16.16b, v17.16b, v18.16b, #8",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vshufpd ymm0, ymm1, ymm2, 1b": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xC6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"ext v16.16b, v17.16b, v18.16b, #8",
|
|
"zip1 v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovaps xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x28 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovaps ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x28 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q16, q2, [x4]",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovaps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x29 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"stp xzr, xzr, [x28, #192]",
|
|
"mov v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"vmovaps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b00 0x29 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"str q2, [x28, #192]",
|
|
"mov v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"vmovapd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x28 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovapd ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x28 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q16, q2, [x4]",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovapd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x29 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"stp xzr, xzr, [x28, #192]",
|
|
"mov v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"vmovapd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0x29 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"str q2, [x28, #192]",
|
|
"mov v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"vmovaps [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b00 0x29 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"vmovaps [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x29 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"stp q16, q2, [x4]"
|
|
]
|
|
},
|
|
"vmovapd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0x29 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"vmovapd [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x29 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"stp q16, q2, [x4]"
|
|
]
|
|
},
|
|
"vcvtsi2ss xmm0, xmm1, eax": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"scvtf s0, w4",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtsi2ss xmm0, xmm1, rax": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"scvtf s0, x4",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtsi2ss xmm0, xmm1, dword [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"mov v16.16b, v17.16b",
|
|
"scvtf s0, s2",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtsi2ss xmm0, xmm1, qword [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x20, [x4]",
|
|
"mov v16.16b, v17.16b",
|
|
"scvtf s0, x20",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtsi2sd xmm0, xmm1, eax": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"scvtf d0, w4",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtsi2sd xmm0, xmm1, rax": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"scvtf d0, x4",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtsi2sd xmm0, xmm1, dword [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x4]",
|
|
"mov v16.16b, v17.16b",
|
|
"scvtf d0, w20",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtsi2sd xmm0, xmm1, qword [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2A 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"mov v16.16b, v17.16b",
|
|
"scvtf d0, d2",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovntps [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b00 0x2B 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"vmovntps [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x2B 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"stnp q16, q2, [x4]"
|
|
]
|
|
},
|
|
"vmovntpd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0x2B 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"vmovntpd [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x2B 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"stnp q16, q2, [x4]"
|
|
]
|
|
},
|
|
"vcvttss2si eax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint32z s2, s16",
|
|
"fcvtzs w4, s2"
|
|
]
|
|
},
|
|
"vcvttss2si rax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint64z s2, s16",
|
|
"fcvtzs x4, s2"
|
|
]
|
|
},
|
|
"vcvttss2si rax, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"frint64z s2, s2",
|
|
"fcvtzs x4, s2"
|
|
]
|
|
},
|
|
"vcvttsd2si eax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint32z d2, d16",
|
|
"fcvtzs w4, d2"
|
|
]
|
|
},
|
|
"vcvttsd2si rax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint64z d2, d16",
|
|
"fcvtzs x4, d2"
|
|
]
|
|
},
|
|
"vcvttsd2si rax, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"frint64z d2, d2",
|
|
"fcvtzs x4, d2"
|
|
]
|
|
},
|
|
"vcvtss2si eax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint32x s2, s16",
|
|
"fcvtzs w4, s2"
|
|
]
|
|
},
|
|
"vcvtss2si rax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint64x s2, s16",
|
|
"fcvtzs x4, s2"
|
|
]
|
|
},
|
|
"vcvtss2si rax, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b10 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"frint64x s2, s2",
|
|
"fcvtzs x4, s2"
|
|
]
|
|
},
|
|
"vcvtsd2si eax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint32x d2, d16",
|
|
"fcvtzs w4, d2"
|
|
]
|
|
},
|
|
"vcvtsd2si rax, xmm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint64x d2, d16",
|
|
"fcvtzs x4, d2"
|
|
]
|
|
},
|
|
"vcvtsd2si rax, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b11 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"frint64x d2, d2",
|
|
"fcvtzs x4, d2"
|
|
]
|
|
},
|
|
"vucomiss xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x2e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmp s16, s17",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"vucomiss xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b00 0x2e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"fcmp s16, s2",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"vucomisd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x2e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmp d16, d17",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"vucomisd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0x2e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"fcmp d16, d2",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"vcomiss xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x2f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmp s16, s17",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"vcomiss xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b00 0x2f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"fcmp s16, s2",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"vcomisd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x2f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmp d16, d17",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"vcomisd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0x2f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"fcmp d16, d2",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
|
|
"csetm x0, eq",
|
|
"ccmn x26, x0, #nzCv, le"
|
|
]
|
|
},
|
|
"vaddps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fadd v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vaddps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x58 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fadd v16.4s, v17.4s, v18.4s",
|
|
"fadd v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vaddpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fadd v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vaddpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x58 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fadd v16.2d, v17.2d, v18.2d",
|
|
"fadd v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vaddss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fadd s0, s17, s18",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vaddsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fadd d0, d17, d18",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmulps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fmul v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmulps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x59 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fmul v16.4s, v17.4s, v18.4s",
|
|
"fmul v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmulpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fmul v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmulpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x59 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fmul v16.2d, v17.2d, v18.2d",
|
|
"fmul v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmulss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fmul s0, s17, s18",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmulsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fmul d0, d17, d18",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtps2pd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcvtl v16.2d, v17.2s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtpd2ps xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"fcvtn v16.2s, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtpd2ps xmm0, yword [rax]": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q2, q3, [x4]",
|
|
"fcvtn v2.2s, v2.2d",
|
|
"fcvtn v3.2s, v3.2d",
|
|
"mov v16.16b, v2.16b",
|
|
"mov v16.d[1], v3.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtpd2ps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcvtn v16.2s, v17.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtss2sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcvt d0, s18",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtss2sd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b10 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x4]",
|
|
"mov v16.16b, v17.16b",
|
|
"fcvt d0, s2",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtsd2ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fcvt s0, d18",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtsd2ss xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b11 0x5a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x4]",
|
|
"mov v16.16b, v17.16b",
|
|
"fcvt s0, d2",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtdq2ps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"scvtf v16.4s, v17.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtdq2ps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"scvtf v16.4s, v17.4s",
|
|
"scvtf v2.4s, v2.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtps2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint32x v2.4s, v17.4s",
|
|
"fcvtzs v16.4s, v2.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtps2dq ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"frint32x v3.4s, v17.4s",
|
|
"fcvtzs v16.4s, v3.4s",
|
|
"frint32x v2.4s, v2.4s",
|
|
"fcvtzs v2.4s, v2.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvttps2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b10 0x5b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint32z v2.4s, v17.4s",
|
|
"fcvtzs v16.4s, v2.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvttps2dq ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b10 0x5b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"frint32z v3.4s, v17.4s",
|
|
"fcvtzs v16.4s, v3.4s",
|
|
"frint32z v2.4s, v2.4s",
|
|
"fcvtzs v2.4s, v2.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vsubps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fsub v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vsubps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fsub v16.4s, v17.4s, v18.4s",
|
|
"fsub v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vsubpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fsub v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vsubpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fsub v16.2d, v17.2d, v18.2d",
|
|
"fsub v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vsubss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x5c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fsub s0, s17, s18",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vsubsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x5c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fsub d0, d17, d18",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vminps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v0.4s, v18.4s, v17.4s",
|
|
"mov v16.16b, v17.16b",
|
|
"bif v16.16b, v18.16b, v0.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vminps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmgt v0.4s, v18.4s, v17.4s",
|
|
"mov v16.16b, v17.16b",
|
|
"bif v16.16b, v18.16b, v0.16b",
|
|
"fcmgt v0.4s, v3.4s, v2.4s",
|
|
"bif v2.16b, v3.16b, v0.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vminpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v0.2d, v18.2d, v17.2d",
|
|
"mov v16.16b, v17.16b",
|
|
"bif v16.16b, v18.16b, v0.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vminpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmgt v0.2d, v18.2d, v17.2d",
|
|
"mov v16.16b, v17.16b",
|
|
"bif v16.16b, v18.16b, v0.16b",
|
|
"fcmgt v0.2d, v3.2d, v2.2d",
|
|
"bif v2.16b, v3.16b, v0.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vminss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b10 0x5d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mrs x20, nzcv",
|
|
"mov v16.16b, v17.16b",
|
|
"fcmp s17, s18",
|
|
"fcsel s0, s17, s18, mi",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"msr nzcv, x20",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vminsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b11 0x5d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mrs x20, nzcv",
|
|
"mov v16.16b, v17.16b",
|
|
"fcmp d17, d18",
|
|
"fcsel d0, d17, d18, mi",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"msr nzcv, x20",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fdiv v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivps ymm0, ymm0, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b00 0x5e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #224]",
|
|
"fdiv v16.4s, v16.4s, v18.4s",
|
|
"fdiv v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivps ymm0, ymm1, ymm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b00 0x5e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #192]",
|
|
"fdiv v16.4s, v17.4s, v16.4s",
|
|
"fdiv v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fdiv v16.4s, v17.4s, v18.4s",
|
|
"fdiv v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fdiv v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivpd ymm0, ymm1, ymm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0x5e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #192]",
|
|
"fdiv v16.2d, v17.2d, v16.2d",
|
|
"fdiv v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivpd ymm0, ymm0, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0x5e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #224]",
|
|
"fdiv v16.2d, v16.2d, v18.2d",
|
|
"fdiv v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fdiv v16.2d, v17.2d, v18.2d",
|
|
"fdiv v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b10 0x5e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fdiv s0, s17, s18",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vdivsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x5e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b",
|
|
"fdiv d0, d17, d18",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmaxps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v0.4s, v17.4s, v18.4s",
|
|
"mov v16.16b, v17.16b",
|
|
"bif v16.16b, v18.16b, v0.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmaxps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"Map 1 0b00 0x5f 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmgt v0.4s, v17.4s, v18.4s",
|
|
"mov v16.16b, v17.16b",
|
|
"bif v16.16b, v18.16b, v0.16b",
|
|
"fcmgt v0.4s, v2.4s, v3.4s",
|
|
"bif v2.16b, v3.16b, v0.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmaxpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v0.2d, v17.2d, v18.2d",
|
|
"mov v16.16b, v17.16b",
|
|
"bif v16.16b, v18.16b, v0.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmaxpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"Map 1 0b01 0x5f 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"fcmgt v0.2d, v17.2d, v18.2d",
|
|
"mov v16.16b, v17.16b",
|
|
"bif v16.16b, v18.16b, v0.16b",
|
|
"fcmgt v0.2d, v2.2d, v3.2d",
|
|
"bif v2.16b, v3.16b, v0.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmaxss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b10 0x5f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mrs x20, nzcv",
|
|
"mov v16.16b, v17.16b",
|
|
"fcmp s17, s18",
|
|
"fcsel s0, s17, s18, gt",
|
|
"mov v16.s[0], v0.s[0]",
|
|
"msr nzcv, x20",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmaxsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b11 0x5f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mrs x20, nzcv",
|
|
"mov v16.16b, v17.16b",
|
|
"fcmp d17, d18",
|
|
"fcsel d0, d17, d18, gt",
|
|
"mov v16.d[0], v0.d[0]",
|
|
"msr nzcv, x20",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckhbw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x68 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckhbw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x68 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"zip2 v16.16b, v17.16b, v18.16b",
|
|
"zip2 v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckhwd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x69 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckhwd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x69 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"zip2 v16.8h, v17.8h, v18.8h",
|
|
"zip2 v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckhdq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckhdq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6a 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"zip2 v16.4s, v17.4s, v18.4s",
|
|
"zip2 v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpackssdw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sqxtn v16.4h, v17.4s",
|
|
"sqxtn2 v16.8h, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpackssdw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sqxtn v16.4h, v17.4s",
|
|
"sqxtn2 v16.8h, v18.4s",
|
|
"sqxtn v2.4h, v2.4s",
|
|
"sqxtn2 v2.8h, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpcklqdq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpcklqdq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"zip1 v16.2d, v17.2d, v18.2d",
|
|
"zip1 v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckhqdq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpunpckhqdq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"zip2 v16.2d, v17.2d, v18.2d",
|
|
"zip2 v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovd xmm0, dword [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovq xmm0, qword [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovdqa xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovdqa [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0x6f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"vmovdqu xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b10 0x6f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovdqu [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b10 0x6f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"vhaddpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x7c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"faddp v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vhaddpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0x7c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"faddp v16.2d, v17.2d, v18.2d",
|
|
"faddp v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vhaddps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b11 0x7c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"faddp v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vhaddps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b11 0x7c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"faddp v16.4s, v17.4s, v18.4s",
|
|
"faddp v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vhsubpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0x7d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uzp1 v2.2d, v17.2d, v18.2d",
|
|
"uzp2 v3.2d, v17.2d, v18.2d",
|
|
"fsub v16.2d, v2.2d, v3.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vhsubpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b01 0x7d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"uzp1 v4.2d, v17.2d, v18.2d",
|
|
"uzp2 v5.2d, v17.2d, v18.2d",
|
|
"fsub v16.2d, v4.2d, v5.2d",
|
|
"uzp1 v4.2d, v2.2d, v3.2d",
|
|
"uzp2 v2.2d, v2.2d, v3.2d",
|
|
"fsub v2.2d, v4.2d, v2.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vhsubps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0x7d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uzp1 v2.4s, v17.4s, v18.4s",
|
|
"uzp2 v3.4s, v17.4s, v18.4s",
|
|
"fsub v16.4s, v2.4s, v3.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vhsubps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b11 0x7d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"uzp1 v4.4s, v17.4s, v18.4s",
|
|
"uzp2 v5.4s, v17.4s, v18.4s",
|
|
"fsub v16.4s, v4.4s, v5.4s",
|
|
"uzp1 v4.4s, v2.4s, v3.4s",
|
|
"uzp2 v2.4s, v2.4s, v3.4s",
|
|
"fsub v2.4s, v4.4s, v2.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovd dword [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0x7e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str s16, [x4]"
|
|
]
|
|
},
|
|
"vmovq qword [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0x7e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str d16, [x4]"
|
|
]
|
|
},
|
|
"vmovdqa ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x7f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q16, q2, [x4]",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovdqa [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0x7f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"stp q16, q2, [x4]"
|
|
]
|
|
},
|
|
"vmovdqu ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b10 0x7f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q16, q2, [x4]",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovdqu [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b10 0x7f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"stp q16, q2, [x4]"
|
|
]
|
|
},
|
|
"vaddsubpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd0 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #3184]",
|
|
"eor v2.16b, v18.16b, v2.16b",
|
|
"fadd v16.2d, v17.2d, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vaddsubpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"ldr q4, [x28, #3184]",
|
|
"eor v5.16b, v18.16b, v4.16b",
|
|
"fadd v16.2d, v17.2d, v5.2d",
|
|
"eor v3.16b, v3.16b, v4.16b",
|
|
"fadd v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vaddsubps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0xd0 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #3152]",
|
|
"eor v2.16b, v18.16b, v2.16b",
|
|
"fadd v16.4s, v17.4s, v2.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vaddsubps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"Map 1 0b11 0xd0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"ldr q4, [x28, #3152]",
|
|
"eor v5.16b, v18.16b, v4.16b",
|
|
"fadd v16.4s, v17.4s, v5.4s",
|
|
"eor v3.16b, v3.16b, v4.16b",
|
|
"fadd v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsrlw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd1 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"neg v0.8h, v0.8h",
|
|
"ushl v16.8h, v17.8h, v0.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsrlw ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd1 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"neg v0.8h, v0.8h",
|
|
"ushl v16.8h, v17.8h, v0.8h",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"neg v0.8h, v0.8h",
|
|
"ushl v2.8h, v2.8h, v0.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsrld xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"neg v0.4s, v0.4s",
|
|
"ushl v16.4s, v17.4s, v0.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsrld ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"neg v0.4s, v0.4s",
|
|
"ushl v16.4s, v17.4s, v0.4s",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"neg v0.4s, v0.4s",
|
|
"ushl v2.4s, v2.4s, v0.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsrlq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd3 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.2d, v0.d[0]",
|
|
"neg v0.2d, v0.2d",
|
|
"ushl v16.2d, v17.2d, v0.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsrlq ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd3 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.2d, v0.d[0]",
|
|
"neg v0.2d, v0.2d",
|
|
"ushl v16.2d, v17.2d, v0.2d",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.2d, v0.d[0]",
|
|
"neg v0.2d, v0.2d",
|
|
"ushl v2.2d, v2.2d, v0.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"add v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd4 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"add v16.2d, v17.2d, v18.2d",
|
|
"add v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmullw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mul v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmullw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd4 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"mul v16.8h, v17.8h, v18.8h",
|
|
"mul v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovq [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str d16, [x4]"
|
|
]
|
|
},
|
|
"vpmovmskb rax, xmm0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd7 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #3408]",
|
|
"cmlt v3.16b, v16.16b, #0",
|
|
"and v2.16b, v3.16b, v2.16b",
|
|
"addp v2.16b, v2.16b, v2.16b",
|
|
"addp v2.16b, v2.16b, v2.16b",
|
|
"addp v2.8b, v2.8b, v2.8b",
|
|
"umov w4, v2.h[0]"
|
|
]
|
|
},
|
|
"vpmovmskb rax, ymm0": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd7 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #3408]",
|
|
"cmlt v4.16b, v16.16b, #0",
|
|
"and v4.16b, v4.16b, v3.16b",
|
|
"addp v4.16b, v4.16b, v4.16b",
|
|
"addp v4.16b, v4.16b, v4.16b",
|
|
"addp v4.8b, v4.8b, v4.8b",
|
|
"umov w20, v4.h[0]",
|
|
"cmlt v2.16b, v2.16b, #0",
|
|
"and v2.16b, v2.16b, v3.16b",
|
|
"addp v2.16b, v2.16b, v2.16b",
|
|
"addp v2.16b, v2.16b, v2.16b",
|
|
"addp v2.8b, v2.8b, v2.8b",
|
|
"umov w21, v2.h[0]",
|
|
"orr x20, x20, x21, lsl #16",
|
|
"mov w4, w20"
|
|
]
|
|
},
|
|
"vpsubusb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd8 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqsub v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubusb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd8 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"uqsub v16.16b, v17.16b, v18.16b",
|
|
"uqsub v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubusw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd9 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqsub v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubusw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xd9 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"uqsub v16.8h, v17.8h, v18.8h",
|
|
"uqsub v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpminub xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xda 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umin v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpminub ymm0, ymm1, ymm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xda 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #192]",
|
|
"umin v16.16b, v17.16b, v16.16b",
|
|
"umin v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpminub ymm0, ymm0, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xda 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #224]",
|
|
"umin v16.16b, v16.16b, v18.16b",
|
|
"umin v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpminub ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xda 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"umin v16.16b, v17.16b, v18.16b",
|
|
"umin v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpand xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xdb 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"and v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpand ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xdb 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"and v16.16b, v17.16b, v18.16b",
|
|
"and v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddusb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xdc 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqadd v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddusb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xdc 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"uqadd v16.16b, v17.16b, v18.16b",
|
|
"uqadd v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddusw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xdd 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqadd v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddusw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xdd 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"uqadd v16.8h, v17.8h, v18.8h",
|
|
"uqadd v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaxub xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xdd 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umax v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaxub ymm0, ymm0, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xde 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #224]",
|
|
"umax v16.16b, v16.16b, v18.16b",
|
|
"umax v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaxub ymm0, ymm1, ymm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xde 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #192]",
|
|
"umax v16.16b, v17.16b, v16.16b",
|
|
"umax v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaxub ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xde 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"umax v16.16b, v17.16b, v18.16b",
|
|
"umax v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpandn xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xdf 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"bic v16.16b, v18.16b, v17.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpandn ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xdf 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"bic v16.16b, v18.16b, v17.16b",
|
|
"bic v2.16b, v3.16b, v2.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpavgb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe0 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"urhadd v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpavgb ymm0, ymm1, ymm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xe0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #192]",
|
|
"urhadd v16.16b, v17.16b, v16.16b",
|
|
"urhadd v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpavgb ymm0, ymm0, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xe0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #224]",
|
|
"urhadd v16.16b, v16.16b, v18.16b",
|
|
"urhadd v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpavgb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"urhadd v16.16b, v17.16b, v18.16b",
|
|
"urhadd v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsraw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe1 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"neg v0.8h, v0.8h",
|
|
"sshl v16.8h, v17.8h, v0.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsraw ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe1 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"neg v0.8h, v0.8h",
|
|
"sshl v16.8h, v17.8h, v0.8h",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"neg v0.8h, v0.8h",
|
|
"sshl v2.8h, v2.8h, v0.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsrad xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"neg v0.4s, v0.4s",
|
|
"sshl v16.4s, v17.4s, v0.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsrad ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"neg v0.4s, v0.4s",
|
|
"sshl v16.4s, v17.4s, v0.4s",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"neg v0.4s, v0.4s",
|
|
"sshl v2.4s, v2.4s, v0.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpavgw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe3 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"urhadd v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpavgw ymm0, ymm1, ymm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xe3 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #192]",
|
|
"urhadd v16.8h, v17.8h, v16.8h",
|
|
"urhadd v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpavgw ymm0, ymm0, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xe3 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #224]",
|
|
"urhadd v16.8h, v16.8h, v18.8h",
|
|
"urhadd v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpavgw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe3 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"urhadd v16.8h, v17.8h, v18.8h",
|
|
"urhadd v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmulhuw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umull2 v0.4s, v17.8h, v18.8h",
|
|
"umull v16.4s, v17.4h, v18.4h",
|
|
"uzp2 v16.8h, v16.8h, v0.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmulhuw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe4 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"umull2 v0.4s, v17.8h, v18.8h",
|
|
"umull v16.4s, v17.4h, v18.4h",
|
|
"uzp2 v16.8h, v16.8h, v0.8h",
|
|
"umull2 v0.4s, v2.8h, v3.8h",
|
|
"umull v2.4s, v2.4h, v3.4h",
|
|
"uzp2 v2.8h, v2.8h, v0.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmulhw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"smull2 v0.4s, v17.8h, v18.8h",
|
|
"smull v16.4s, v17.4h, v18.4h",
|
|
"uzp2 v16.8h, v16.8h, v0.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmulhw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe5 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"smull2 v0.4s, v17.8h, v18.8h",
|
|
"smull v16.4s, v17.4h, v18.4h",
|
|
"uzp2 v16.8h, v16.8h, v0.8h",
|
|
"smull2 v0.4s, v2.8h, v3.8h",
|
|
"smull v2.4s, v2.4h, v3.4h",
|
|
"uzp2 v2.8h, v2.8h, v0.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvttpd2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint32z v2.2d, v17.2d",
|
|
"fcvtzs v2.2d, v2.2d",
|
|
"xtn v16.2s, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvttpd2dq xmm0, ymm1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"frint32z v3.2d, v17.2d",
|
|
"fcvtzs v3.2d, v3.2d",
|
|
"xtn v3.2s, v3.2d",
|
|
"frint32z v2.2d, v2.2d",
|
|
"fcvtzs v2.2d, v2.2d",
|
|
"xtn v2.2s, v2.2d",
|
|
"zip1 v16.2d, v3.2d, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtdq2pd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Map 1 0b10 0xe6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sxtl v2.2d, v17.2s",
|
|
"scvtf v16.2d, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtdq2pd ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b10 0xe6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sxtl v2.2d, v17.2s",
|
|
"scvtf v16.2d, v2.2d",
|
|
"sxtl2 v2.2d, v17.4s",
|
|
"scvtf v2.2d, v2.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtpd2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b11 0xe6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"frint32x v2.2d, v17.2d",
|
|
"fcvtzs v2.2d, v2.2d",
|
|
"xtn v16.2s, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vcvtpd2dq xmm0, ymm1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b11 0xe6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"frint32x v3.2d, v17.2d",
|
|
"fcvtzs v3.2d, v3.2d",
|
|
"xtn v3.2s, v3.2d",
|
|
"frint32x v2.2d, v2.2d",
|
|
"fcvtzs v2.2d, v2.2d",
|
|
"xtn v2.2s, v2.2d",
|
|
"zip1 v16.2d, v3.2d, v2.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vmovntdq [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe7 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"vmovntdq [rax], ymm0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe7 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"stnp q16, q2, [x4]"
|
|
]
|
|
},
|
|
"vpsubsb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe8 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sqsub v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubsb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe8 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sqsub v16.16b, v17.16b, v18.16b",
|
|
"sqsub v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe9 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sqsub v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xe9 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sqsub v16.8h, v17.8h, v18.8h",
|
|
"sqsub v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpminsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xea 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"smin v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpminsw ymm0, ymm1, ymm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xea 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #192]",
|
|
"smin v16.8h, v17.8h, v16.8h",
|
|
"smin v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpminsw ymm0, ymm0, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xea 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #224]",
|
|
"smin v16.8h, v16.8h, v18.8h",
|
|
"smin v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpminsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xea 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"smin v16.8h, v17.8h, v18.8h",
|
|
"smin v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpor xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xeb 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"orr v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpor ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xeb 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"orr v16.16b, v17.16b, v18.16b",
|
|
"orr v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddsb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xec 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sqadd v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddsb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xec 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sqadd v16.16b, v17.16b, v18.16b",
|
|
"sqadd v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xed 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sqadd v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xed 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sqadd v16.8h, v17.8h, v18.8h",
|
|
"sqadd v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaxsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xee 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"smax v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaxsw ymm0, ymm1, ymm0": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xee 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #192]",
|
|
"smax v16.8h, v17.8h, v16.8h",
|
|
"smax v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaxsw ymm0, ymm0, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Aliasing source and destination",
|
|
"Map 1 0b01 0xee 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #224]",
|
|
"smax v16.8h, v16.8h, v18.8h",
|
|
"smax v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaxsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xee 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"smax v16.8h, v17.8h, v18.8h",
|
|
"smax v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpxor xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xef 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"eor v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpxor ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xef 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"eor v16.16b, v17.16b, v18.16b",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpxor xmm0, xmm1, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"xor with itself to get zero register",
|
|
"Map 1 0b01 0xef 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v16.2d, #0x0",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpxor ymm0, ymm1, ymm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"xor with itself to get zero register",
|
|
"Map 1 0b01 0xef 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v16.2d, #0x0",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vlddqu xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b11 0xf0 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vlddqu ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b11 0xf0 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldp q16, q2, [x4]",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsllw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf1 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"ushl v16.8h, v17.8h, v0.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsllw ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf1 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"ushl v16.8h, v17.8h, v0.8h",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"ushl v2.8h, v2.8h, v0.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpslld xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf2 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"ushl v16.4s, v17.4s, v0.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpslld ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf2 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"ushl v16.4s, v17.4s, v0.4s",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"ushl v2.4s, v2.4s, v0.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsllq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf3 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.2d, v0.d[0]",
|
|
"ushl v16.2d, v17.2d, v0.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsllq ymm0, ymm1, xmm2": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf3 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.2d, v0.d[0]",
|
|
"ushl v16.2d, v17.2d, v0.2d",
|
|
"uqshl d0, d18, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.2d, v0.d[0]",
|
|
"ushl v2.2d, v2.2d, v0.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmuludq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf4 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uzp1 v2.4s, v17.4s, v17.4s",
|
|
"uzp1 v3.4s, v18.4s, v18.4s",
|
|
"umull v16.2d, v2.2s, v3.2s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmuludq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf4 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"uzp1 v4.4s, v17.4s, v17.4s",
|
|
"uzp1 v5.4s, v18.4s, v18.4s",
|
|
"umull v16.2d, v4.2s, v5.2s",
|
|
"uzp1 v2.4s, v2.4s, v2.4s",
|
|
"uzp1 v3.4s, v3.4s, v3.4s",
|
|
"umull v2.2d, v2.2s, v3.2s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaddwd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf5 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"smull v2.4s, v17.4h, v18.4h",
|
|
"smull2 v3.4s, v17.8h, v18.8h",
|
|
"addp v16.4s, v2.4s, v3.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaddwd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf5 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"smull v4.4s, v17.4h, v18.4h",
|
|
"smull2 v5.4s, v17.8h, v18.8h",
|
|
"addp v16.4s, v4.4s, v5.4s",
|
|
"smull v4.4s, v2.4h, v3.4h",
|
|
"smull2 v2.4s, v2.8h, v3.8h",
|
|
"addp v2.4s, v4.4s, v2.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsadbw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf6 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uabdl v2.8h, v17.8b, v18.8b",
|
|
"uabdl2 v3.8h, v17.16b, v18.16b",
|
|
"addv h2, v2.8h",
|
|
"addv h3, v3.8h",
|
|
"zip1 v16.2d, v2.2d, v3.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsadbw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf6 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"uabdl v4.8h, v17.8b, v18.8b",
|
|
"uabdl2 v5.8h, v17.16b, v18.16b",
|
|
"addv h4, v4.8h",
|
|
"addv h5, v5.8h",
|
|
"zip1 v16.2d, v4.2d, v5.2d",
|
|
"uabdl v4.8h, v2.8b, v3.8b",
|
|
"uabdl2 v2.8h, v2.16b, v3.16b",
|
|
"addv h3, v4.8h",
|
|
"addv h2, v2.8h",
|
|
"zip1 v2.2d, v3.2d, v2.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vmaskmovdqu xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf7 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cmlt v2.16b, v17.16b, #0",
|
|
"ldr q3, [x11]",
|
|
"bsl v2.16b, v16.16b, v3.16b",
|
|
"str q2, [x11]"
|
|
]
|
|
},
|
|
"vpsubb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf8 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sub v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf8 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sub v16.16b, v17.16b, v18.16b",
|
|
"sub v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf9 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sub v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xf9 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sub v16.8h, v17.8h, v18.8h",
|
|
"sub v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfa 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sub v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfa 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sub v16.4s, v17.4s, v18.4s",
|
|
"sub v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfb 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sub v16.2d, v17.2d, v18.2d",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpsubq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfb 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"sub v16.2d, v17.2d, v18.2d",
|
|
"sub v2.2d, v2.2d, v3.2d",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfc 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"add v16.16b, v17.16b, v18.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfc 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"add v16.16b, v17.16b, v18.16b",
|
|
"add v2.16b, v2.16b, v3.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfd 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"add v16.8h, v17.8h, v18.8h",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfd 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"add v16.8h, v17.8h, v18.8h",
|
|
"add v2.8h, v2.8h, v3.8h",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfe 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"add v16.4s, v17.4s, v18.4s",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpaddd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"Map 1 0b01 0xfe 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"ldr q3, [x28, #224]",
|
|
"add v16.4s, v17.4s, v18.4s",
|
|
"add v2.4s, v2.4s, v3.4s",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
}
|
|
}
|
|
}
|