Alyssa Rosenzweig 4d13f5d97d IR: Add Orlshl op ...

On arm64, orr (with a shifted register) is maybe fewer cycles and
definitely easier on the RA than bfi (=> fewer moves generated). So,
it's preferred when we know the corresponding bit is 0 in the
destination.

It's not useful on other targets, so it's gated behind a backend feature
bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2023-08-02 12:38:00 -04:00

..

Config

FEXCore: Remove erroneous asserts in the project

2023-07-28 13:36:05 -07:00

Context

Context: Make alias for code invalidation functor

2023-07-27 18:59:15 -04:00

Core

IR: Add Orlshl op

2023-08-02 12:38:00 -04:00

GDBJIT

SourcecodeResolver: Convert string to fextl

2023-03-16 03:21:45 -07:00

HLE/Thunks

Thunks: Mostly reverts #2672

2023-05-18 15:50:55 -07:00

IR

IR: Add Orlshl op

2023-08-02 12:38:00 -04:00