mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 10:00:16 +02:00
411 lines
10 KiB
JSON
411 lines
10 KiB
JSON
{
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"Features": {
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"Bitness": 32,
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"EnabledHostFeatures": [],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"AFP",
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"FlagM",
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"FlagM2"
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],
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"BinaryCacheVersion": 21
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},
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"Instructions": {
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"push es": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x06",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #960]",
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"str w20, [x8, #-4]!"
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]
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},
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"pop es": {
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"ExpectedInstructionCount": 12,
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"Comment": "0x07",
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"ExpectedArm64ASM": [
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"ldr w20, [x8], #4",
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"strh w20, [x28, #960]",
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"ubfx w21, w20, #2, #1",
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"and w20, w20, #0xfff8",
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"add x0, x28, x21, lsl #3",
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"ldr x21, [x0, #1184]",
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"ldr x20, [x21, w20, uxtw]",
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"lsr x21, x20, #32",
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"and w22, w21, #0xff000000",
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"orr w20, w22, w20, lsr #16",
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"bfi w20, w21, #16, #8",
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"str w20, [x28, #976]"
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]
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},
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"push cs": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x0e",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #962]",
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"str w20, [x8, #-4]!"
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]
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},
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"push ss": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x16",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #964]",
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"str w20, [x8, #-4]!"
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]
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},
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"pop ss": {
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"ExpectedInstructionCount": 22,
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"Comment": "0x17",
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"ExpectedArm64ASM": [
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"ldr w20, [x8], #4",
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"ldrb w21, [x28, #1016]",
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"mov w22, #0x1",
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"and w21, w21, #0x1",
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"ldrb w23, [x28, #1016]",
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"and w23, w23, #0xfffffffe",
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"mrs x12, nzcv",
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"cmp x21, #0x0 (0)",
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"csel x21, x23, x22, eq",
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"strb w21, [x28, #1016]",
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"strh w20, [x28, #964]",
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"ubfx w21, w20, #2, #1",
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"and w20, w20, #0xfff8",
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"add x0, x28, x21, lsl #3",
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"ldr x21, [x0, #1184]",
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"ldr x20, [x21, w20, uxtw]",
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"lsr x21, x20, #32",
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"and w22, w21, #0xff000000",
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"orr w20, w22, w20, lsr #16",
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"bfi w20, w21, #16, #8",
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"str w20, [x28, #984]",
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"msr nzcv, x12"
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]
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},
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"push ds": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x1e",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #966]",
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"str w20, [x8, #-4]!"
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]
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},
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"pop ds": {
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"ExpectedInstructionCount": 12,
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"Comment": "0x1f",
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"ExpectedArm64ASM": [
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"ldr w20, [x8], #4",
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"strh w20, [x28, #966]",
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"ubfx w21, w20, #2, #1",
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"and w20, w20, #0xfff8",
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"add x0, x28, x21, lsl #3",
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"ldr x21, [x0, #1184]",
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"ldr x20, [x21, w20, uxtw]",
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"lsr x21, x20, #32",
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"and w22, w21, #0xff000000",
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"orr w20, w22, w20, lsr #16",
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"bfi w20, w21, #16, #8",
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"str w20, [x28, #988]"
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]
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},
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"daa": {
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"ExpectedInstructionCount": 23,
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"Comment": "0x27",
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"ExpectedArm64ASM": [
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"uxtb w20, w4",
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"cset x21, hs",
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"and x22, x20, #0xf",
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"cmp x22, #0x9 (9)",
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"cset x22, hi",
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"eor x23, x27, x26",
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"ubfx w23, w23, #4, #1",
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"orr x22, x23, x22",
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"cmp x20, #0x99 (153)",
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"cset x23, ls",
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"and x21, x21, x23",
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"add x23, x20, #0x6 (6)",
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"cmp x22, #0x0 (0)",
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"csel x20, x23, x20, ne",
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"add x23, x20, #0x60 (96)",
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"cmp x21, #0x0 (0)",
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"csel x26, x23, x20, eq",
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"bfxil x4, x26, #0, #8",
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"cmn wzr, w26, lsl #24",
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"mrs x20, nzcv",
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"bfi w20, w21, #29, #1",
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"eor w27, w26, w22, lsl #4",
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"msr nzcv, x20"
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]
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},
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"das": {
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"ExpectedInstructionCount": 27,
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"Comment": "0x2f",
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"ExpectedArm64ASM": [
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"uxtb w20, w4",
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"cset x21, lo",
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"and x22, x20, #0xf",
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"cmp x22, #0x9 (9)",
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"cset x22, hi",
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"eor x23, x27, x26",
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"ubfx w23, w23, #4, #1",
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"orr x22, x23, x22",
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"cmp x20, #0x99 (153)",
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"cset x23, hi",
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"orr x21, x21, x23",
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"cmp x20, #0x6 (6)",
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"csel x23, x22, x21, lo",
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"orr w23, w21, w23",
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"sub x12, x20, #0x6 (6)",
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"cmp x22, #0x0 (0)",
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"csel x20, x12, x20, ne",
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"sub x12, x20, #0x60 (96)",
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"cmp x21, #0x0 (0)",
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"csel x26, x12, x20, ne",
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"bfxil x4, x26, #0, #8",
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"cmn wzr, w26, lsl #24",
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"eor x20, x23, #0x1",
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"mrs x21, nzcv",
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"bfi w21, w20, #29, #1",
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"eor w27, w26, w22, lsl #4",
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"msr nzcv, x21"
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]
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},
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"aaa": {
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"ExpectedInstructionCount": 13,
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"Comment": "0x37",
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"ExpectedArm64ASM": [
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"and x20, x4, #0xf",
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"cmp x20, #0x9 (9)",
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"cset x20, hi",
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"eor x21, x27, x26",
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"ubfx w21, w21, #4, #1",
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"orr x20, x21, x20",
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"cmp wzr, w20",
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"eor w27, w26, w20, lsl #4",
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"add w20, w4, #0x106 (262)",
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"csel w20, w20, w4, lo",
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"mov w21, #0xff0f",
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"and w20, w20, w21",
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"bfxil x4, x20, #0, #16"
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]
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},
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"aas": {
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"ExpectedInstructionCount": 13,
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"Comment": "0x3f",
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"ExpectedArm64ASM": [
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"and x20, x4, #0xf",
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"cmp x20, #0x9 (9)",
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"cset x20, hi",
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"eor x21, x27, x26",
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"ubfx w21, w21, #4, #1",
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"orr x20, x21, x20",
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"cmp wzr, w20",
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"eor w27, w26, w20, lsl #4",
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"sub w20, w4, #0x106 (262)",
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"csel w20, w20, w4, lo",
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"mov w21, #0xff0f",
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"and w20, w20, w21",
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"bfxil x4, x20, #0, #16"
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]
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},
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"inc ax": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x40",
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"ExpectedArm64ASM": [
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"uxth w27, w4",
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"mov w20, #0x1",
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"cset x21, hs",
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"lsl w0, w27, #16",
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"cmn w0, w20, lsl #16",
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"add w26, w27, #0x1 (1)",
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"mrs x20, nzcv",
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"bfi w20, w21, #29, #1",
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"bfxil x4, x26, #0, #16",
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"msr nzcv, x20"
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]
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},
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"inc eax": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x40",
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"ExpectedArm64ASM": [
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"cset x20, hs",
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"adds w26, w4, #0x1 (1)",
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"mrs x21, nzcv",
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"bfi w21, w20, #29, #1",
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"msr nzcv, x21",
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"mov x27, x4",
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"mov x4, x26"
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]
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},
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"dec ax": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x48",
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"ExpectedArm64ASM": [
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"uxth w27, w4",
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"mov w20, #0x1",
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"cset x21, hs",
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"lsl w0, w27, #16",
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"cmp w0, w20, lsl #16",
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"sub w26, w27, #0x1 (1)",
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"mrs x20, nzcv",
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"bfi w20, w21, #29, #1",
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"bfxil x4, x26, #0, #16",
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"msr nzcv, x20"
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]
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},
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"push ax": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x50",
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"ExpectedArm64ASM": [
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"strh w4, [x8, #-2]!"
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]
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},
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"push eax": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x50",
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"ExpectedArm64ASM": [
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"str w4, [x8, #-4]!"
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]
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},
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"dec eax": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x48",
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"ExpectedArm64ASM": [
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"cset x20, hs",
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"subs w26, w4, #0x1 (1)",
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"mrs x21, nzcv",
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"bfi w21, w20, #29, #1",
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"msr nzcv, x21",
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"mov x27, x4",
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"mov x4, x26"
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]
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},
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"pusha": {
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"ExpectedInstructionCount": 5,
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"Comment": "0x60",
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"ExpectedArm64ASM": [
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"mov x20, x8",
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"stp w7, w4, [x8, #-8]!",
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"stp w6, w5, [x8, #-8]!",
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"stp w9, w20, [x8, #-8]!",
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"stp w11, w10, [x8, #-8]!"
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]
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},
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"pushad": {
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"ExpectedInstructionCount": 5,
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"Comment": "0x60",
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"ExpectedArm64ASM": [
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"mov x20, x8",
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"stp w7, w4, [x8, #-8]!",
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"stp w6, w5, [x8, #-8]!",
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"stp w9, w20, [x8, #-8]!",
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"stp w11, w10, [x8, #-8]!"
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]
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},
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"popa": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x61",
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"ExpectedArm64ASM": [
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"mov x20, x8",
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"ldp w11, w10, [x20], #8",
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"ldr w9, [x20], #4",
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"add x20, x20, #0x4 (4)",
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"mov x8, x20",
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"ldp w6, w5, [x8], #8",
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"ldp w7, w4, [x8], #8"
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]
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},
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"popad": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x61",
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"ExpectedArm64ASM": [
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"mov x20, x8",
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"ldp w11, w10, [x20], #8",
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"ldr w9, [x20], #4",
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"add x20, x20, #0x4 (4)",
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"mov x8, x20",
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"ldp w6, w5, [x8], #8",
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"ldp w7, w4, [x8], #8"
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]
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},
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"aam": {
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"ExpectedInstructionCount": 10,
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"Comment": "0xd4",
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"ExpectedArm64ASM": [
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"uxtb w20, w4",
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"mov w21, #0xa",
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"udiv x22, x20, x21",
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"msub x12, x22, x21, x20",
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"add x26, x12, x22, lsl #8",
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"bfxil x4, x26, #0, #16",
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"cmn wzr, w26, lsl #24",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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]
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},
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"aad": {
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"ExpectedInstructionCount": 10,
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"Comment": "0xd5",
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"ExpectedArm64ASM": [
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"lsr w20, w4, #8",
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"mov w21, #0xa",
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"mul x20, x20, x21",
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"add x20, x4, x20",
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"and x26, x20, #0xff",
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"bfxil x4, x26, #0, #16",
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"cmn wzr, w26, lsl #24",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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]
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},
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"db 0xd4, 0x40": {
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"ExpectedInstructionCount": 10,
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"Comment": [
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"aam with a different immediate byte base",
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"0xd4"
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],
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"ExpectedArm64ASM": [
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"uxtb w20, w4",
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"mov w21, #0x40",
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"udiv x22, x20, x21",
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"msub x12, x22, x21, x20",
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"add x26, x12, x22, lsl #8",
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"bfxil x4, x26, #0, #16",
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"cmn wzr, w26, lsl #24",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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]
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},
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"db 0xd5, 0x40": {
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"ExpectedInstructionCount": 10,
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"Comment": [
|
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"aad with a different immediate byte base",
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"0xd5"
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],
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"ExpectedArm64ASM": [
|
|
"lsr w20, w4, #8",
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"mov w21, #0x40",
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"mul x20, x20, x21",
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"add x20, x4, x20",
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"and x26, x20, #0xff",
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"bfxil x4, x26, #0, #16",
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"cmn wzr, w26, lsl #24",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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]
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},
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"salc": {
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"ExpectedInstructionCount": 2,
|
|
"Comment": "0xd6",
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|
"ExpectedArm64ASM": [
|
|
"csetm w20, lo",
|
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"bfxil x4, x20, #0, #8"
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]
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}
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}
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}
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