Alyssa Rosenzweig 46ca53ad0d Merge pull request #3704 from alyssarosenzweig/ra/spill-better ...

RA: priorize remat over spilling

2024-06-17 09:01:50 -04:00

..

Config

Config: Change default TSO options

2024-05-21 18:08:58 -07:00

Context

Core: Clean up ownership management for IRListView and RegisterAllocationData

2024-05-21 17:51:17 +02:00

Core

Merge pull request #3712 from alyssarosenzweig/jit/silly-assert

2024-06-17 08:59:00 -04:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

HLE/Thunks

IR: specify registers, not offsets for SRA

2024-05-08 14:01:42 -04:00

IR

RegisterAllocationPass: optimize spill loop

2024-06-16 08:15:15 -04:00