mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-07 04:05:14 +02:00
Ryan Houdek
3f9df49e3e
Taking this very slowly because this is very fickle code. The frontend needs to manage GDT and LDT, but before we get there, we need to actually add support for LDT in the backend. Split the segments to two arrays so the JIT can actually update their cached values correctly. Still treats GDT and LDT as mirrors like how the JIT previously did (By it ignoring the selector's TI bit).
368 lines
14 KiB
C++
368 lines
14 KiB
C++
// SPDX-License-Identifier: MIT
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/*
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$info$
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tags: LinuxSyscalls|syscalls-x86-32
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$end_info$
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*/
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#include "ArchHelpers/UContext.h"
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#include "LinuxSyscalls/SignalDelegator.h"
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#include "LinuxSyscalls/Syscalls.h"
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#include "LinuxSyscalls/x32/Syscalls.h"
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#include "LinuxSyscalls/x32/Thread.h"
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#include "LinuxSyscalls/x32/Types.h"
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#include "LinuxSyscalls/x64/Syscalls.h"
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#include <FEXCore/Core/CoreState.h>
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#include <FEXCore/Debug/InternalThreadState.h>
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#include <FEXCore/fextl/vector.h>
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#include <errno.h>
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#include <grp.h>
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#include <linux/futex.h>
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#include <sched.h>
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#include <signal.h>
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#include <sys/fsuid.h>
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#include <sys/resource.h>
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#include <sys/wait.h>
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#include <syscall.h>
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#include <time.h>
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#include <unistd.h>
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ARG_TO_STR(FEX::HLE::x32::compat_ptr<FEX::HLE::x32::stack_t32>, "%x")
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ARG_TO_STR(FEX::HLE::x32::compat_ptr<FEXCore::x86::siginfo_t>, "%x")
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namespace FEX::HLE::x32 {
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// The kernel only gives 32-bit userspace 3 TLS segments
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// Depending on if the host kernel is 32-bit or 64-bit then the TLS index assigned is different
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//
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// Host kernel x86_64, valid TLS enries: 12,13,14
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// Host kernel x86, valid TLS enries: 6,7,8
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// Since we are claiming to be a 64-bit kernel, use the 64-bit range
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//
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// 6/12 = glibc
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// 7/13 = wine fs
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// 8/14 = etc
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constexpr uint32_t TLS_NextEntry = 12;
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constexpr uint32_t TLS_MaxEntry = TLS_NextEntry + 3;
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uint64_t SetThreadArea(FEXCore::Core::CpuStateFrame* Frame, void* tls) {
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struct x32::user_desc* u_info = reinterpret_cast<struct x32::user_desc*>(tls);
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FaultSafeUserMemAccess::VerifyIsReadable(u_info, sizeof(*u_info));
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if (u_info->entry_number == -1) {
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for (uint32_t i = TLS_NextEntry; i < TLS_MaxEntry; ++i) {
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auto GDT = &Frame->State.segment_arrays[0][i];
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if (Frame->State.CalculateGDTLimit(*GDT) == 0) {
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// If the limit is zero then it isn't present with our setup
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u_info->entry_number = i;
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break;
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}
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}
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if (u_info->entry_number == -1) {
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// Couldn't find a slot. Return empty handed
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return -ESRCH;
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}
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}
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// Now we need to update the thread's GDT to handle this change
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auto GDT = &Frame->State.segment_arrays[0][u_info->entry_number];
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Frame->State.SetGDTBase(GDT, u_info->base_addr);
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Frame->State.SetGDTLimit(GDT, 0xF'FFFFU);
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// With the segment register optimization we need to check all of the segment registers and update.
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const auto GetEntry = [](auto value) {
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return value >> 3;
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};
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if (GetEntry(Frame->State.cs_idx) == u_info->entry_number) {
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Frame->State.cs_cached = Frame->State.CalculateGDTBase(*GDT);
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}
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if (GetEntry(Frame->State.ds_idx) == u_info->entry_number) {
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Frame->State.ds_cached = Frame->State.CalculateGDTBase(*GDT);
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}
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if (GetEntry(Frame->State.es_idx) == u_info->entry_number) {
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Frame->State.es_cached = Frame->State.CalculateGDTBase(*GDT);
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}
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if (GetEntry(Frame->State.fs_idx) == u_info->entry_number) {
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Frame->State.fs_cached = Frame->State.CalculateGDTBase(*GDT);
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}
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if (GetEntry(Frame->State.gs_idx) == u_info->entry_number) {
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Frame->State.gs_cached = Frame->State.CalculateGDTBase(*GDT);
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}
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if (GetEntry(Frame->State.ss_idx) == u_info->entry_number) {
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Frame->State.ss_cached = Frame->State.CalculateGDTBase(*GDT);
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}
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return 0;
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}
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void AdjustRipForNewThread(FEXCore::Core::CpuStateFrame* Frame) {
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Frame->State.rip += 2;
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}
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void RegisterThread(FEX::HLE::SyscallHandler* Handler) {
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REGISTER_SYSCALL_IMPL_X32(sigreturn, [](FEXCore::Core::CpuStateFrame* Frame) -> uint64_t {
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FEX::HLE::_SyscallHandler->GetSignalDelegator()->HandleSignalHandlerReturn(false);
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FEX_UNREACHABLE;
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});
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REGISTER_SYSCALL_IMPL_X32(
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clone, ([](FEXCore::Core::CpuStateFrame* Frame, uint32_t flags, void* stack, pid_t* parent_tid, void* tls, pid_t* child_tid) -> uint64_t {
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// This is slightly different EFAULT behaviour, if child_tid or parent_tid is invalid then the kernel just doesn't write to the
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// pointer. Still need to be EFAULT safe although.
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if ((flags & (CLONE_CHILD_SETTID | CLONE_CHILD_CLEARTID)) && child_tid) {
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FaultSafeUserMemAccess::VerifyIsWritable(child_tid, sizeof(*child_tid));
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}
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if ((flags & CLONE_PARENT_SETTID) && parent_tid) {
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FaultSafeUserMemAccess::VerifyIsWritable(parent_tid, sizeof(*parent_tid));
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}
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FEX::HLE::clone3_args args {.Type = TypeOfClone::TYPE_CLONE2,
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.args = {
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.flags = flags & ~CSIGNAL, // This no longer contains CSIGNAL
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.pidfd = reinterpret_cast<uint64_t>(parent_tid), // For clone, pidfd is duplicated here
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.child_tid = reinterpret_cast<uint64_t>(child_tid),
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.parent_tid = reinterpret_cast<uint64_t>(parent_tid),
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.exit_signal = flags & CSIGNAL,
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.stack = reinterpret_cast<uint64_t>(stack),
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.stack_size = 0, // This syscall isn't able to see the stack size
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.tls = reinterpret_cast<uint64_t>(tls),
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.set_tid = 0, // This syscall isn't able to select TIDs
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.set_tid_size = 0,
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.cgroup = 0, // This syscall can't select cgroups
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}};
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return CloneHandler(Frame, &args);
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}));
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REGISTER_SYSCALL_IMPL_X32(waitpid, [](FEXCore::Core::CpuStateFrame* Frame, pid_t pid, int32_t* status, int32_t options) -> uint64_t {
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uint64_t Result = ::waitpid(pid, status, options);
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FaultSafeUserMemAccess::VerifyIsWritableOrNull(status, sizeof(*status));
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SYSCALL_ERRNO();
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});
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REGISTER_SYSCALL_IMPL_X32(nice, [](FEXCore::Core::CpuStateFrame* Frame, int inc) -> uint64_t {
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uint64_t Result = ::nice(inc);
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SYSCALL_ERRNO();
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});
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REGISTER_SYSCALL_IMPL_X32(
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set_thread_area, [](FEXCore::Core::CpuStateFrame* Frame, struct user_desc* u_info) -> uint64_t { return SetThreadArea(Frame, u_info); });
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REGISTER_SYSCALL_IMPL_X32(get_thread_area, [](FEXCore::Core::CpuStateFrame* Frame, struct user_desc* u_info) -> uint64_t {
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// Index to fetch comes from the user_desc
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uint32_t Entry = u_info->entry_number;
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if (Entry < TLS_NextEntry || Entry > TLS_MaxEntry) {
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return -EINVAL;
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}
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FaultSafeUserMemAccess::VerifyIsWritable(u_info, sizeof(*u_info));
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const auto& GDT = &Frame->State.segment_arrays[0][Entry];
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memset(u_info, 0, sizeof(*u_info));
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// FEX only stores base instead of the full GDT
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u_info->base_addr = Frame->State.CalculateGDTBase(*GDT);
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// Fill the rest of the structure with expected data (even if wrong at the moment)
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if (u_info->base_addr) {
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u_info->limit = 0xF'FFFF;
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u_info->seg_32bit = 1;
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u_info->limit_in_pages = 1;
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u_info->useable = 1;
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} else {
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u_info->read_exec_only = 1;
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u_info->seg_not_present = 1;
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}
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return 0;
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});
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REGISTER_SYSCALL_IMPL_X32(set_robust_list, [](FEXCore::Core::CpuStateFrame* Frame, struct robust_list_head* head, size_t len) -> uint64_t {
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if (len != 12) {
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// Return invalid if the passed in length doesn't match what's expected.
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return -EINVAL;
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}
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auto ThreadObject = FEX::HLE::ThreadManager::GetStateObjectFromCPUState(Frame);
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// Retain the robust list head but don't give it to the kernel
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// The kernel would break if it tried parsing a 32bit robust list from a 64bit process
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ThreadObject->ThreadInfo.robust_list_head = reinterpret_cast<uint64_t>(head);
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return 0;
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});
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REGISTER_SYSCALL_IMPL_X32(
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get_robust_list, [](FEXCore::Core::CpuStateFrame* Frame, int pid, struct robust_list_head** head, uint32_t* len_ptr) -> uint64_t {
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FaultSafeUserMemAccess::VerifyIsWritable(head, sizeof(uint32_t));
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FaultSafeUserMemAccess::VerifyIsWritable(len_ptr, sizeof(*len_ptr));
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auto ThreadObject = FEX::HLE::ThreadManager::GetStateObjectFromCPUState(Frame);
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// Give the robust list back to the application
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// Steam specifically checks to make sure the robust list is set
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*(uint32_t*)head = (uint32_t)ThreadObject->ThreadInfo.robust_list_head;
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*len_ptr = 12;
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return 0;
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});
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REGISTER_SYSCALL_IMPL_X32(
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futex, [](FEXCore::Core::CpuStateFrame* Frame, int* uaddr, int futex_op, int val, const timespec32* timeout, int* uaddr2, uint32_t val3) -> uint64_t {
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void* timeout_ptr = (void*)timeout;
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struct timespec tp64 {};
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int cmd = futex_op & FUTEX_CMD_MASK;
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if (timeout && (cmd == FUTEX_WAIT || cmd == FUTEX_LOCK_PI || cmd == FUTEX_WAIT_BITSET || cmd == FUTEX_WAIT_REQUEUE_PI)) {
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FaultSafeUserMemAccess::VerifyIsReadable(timeout, sizeof(*timeout));
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// timeout argument is only handled as timespec in these cases
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// Otherwise just an integer
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tp64 = *timeout;
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timeout_ptr = &tp64;
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}
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uint64_t Result = syscall(SYSCALL_DEF(futex), uaddr, futex_op, val, timeout_ptr, uaddr2, val3);
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SYSCALL_ERRNO();
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});
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REGISTER_SYSCALL_IMPL_X32(
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sigaltstack, [](FEXCore::Core::CpuStateFrame* Frame, const compat_ptr<stack_t32> ss, compat_ptr<stack_t32> old_ss) -> uint64_t {
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stack_t ss64 {};
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stack_t old64 {};
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stack_t* ss64_ptr {};
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stack_t* old64_ptr {};
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if (ss) {
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FaultSafeUserMemAccess::VerifyIsReadable(ss, sizeof(*ss));
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ss64 = *ss;
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ss64_ptr = &ss64;
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}
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if (old_ss) {
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FaultSafeUserMemAccess::VerifyIsReadable(old_ss, sizeof(*old_ss));
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old64 = *old_ss;
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old64_ptr = &old64;
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}
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uint64_t Result = FEX::HLE::_SyscallHandler->GetSignalDelegator()->RegisterGuestSigAltStack(
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FEX::HLE::ThreadManager::GetStateObjectFromCPUState(Frame), ss64_ptr, old64_ptr);
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if (Result == 0 && old_ss) {
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FaultSafeUserMemAccess::VerifyIsWritable(old_ss, sizeof(*old_ss));
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*old_ss = old64;
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}
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return Result;
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});
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// launch a new process under fex
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// currently does not propagate argv[0] correctly
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REGISTER_SYSCALL_IMPL_X32(execve, [](FEXCore::Core::CpuStateFrame* Frame, const char* pathname, uint32_t* argv, uint32_t* envp) -> uint64_t {
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fextl::vector<const char*> Args;
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fextl::vector<const char*> Envp;
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if (argv) {
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for (int i = 0; argv[i]; i++) {
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Args.push_back(reinterpret_cast<const char*>(static_cast<uintptr_t>(argv[i])));
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}
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Args.push_back(nullptr);
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}
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if (envp) {
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for (int i = 0; envp[i]; i++) {
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Envp.push_back(reinterpret_cast<const char*>(static_cast<uintptr_t>(envp[i])));
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}
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Envp.push_back(nullptr);
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}
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auto* const* ArgsPtr = argv ? const_cast<char* const*>(Args.data()) : nullptr;
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auto* const* EnvpPtr = envp ? const_cast<char* const*>(Envp.data()) : nullptr;
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FEX::HLE::ExecveAtArgs AtArgs = FEX::HLE::ExecveAtArgs::Empty();
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return FEX::HLE::ExecveHandler(Frame, pathname, ArgsPtr, EnvpPtr, AtArgs);
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});
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REGISTER_SYSCALL_IMPL_X32(
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execveat, ([](FEXCore::Core::CpuStateFrame* Frame, int dirfd, const char* pathname, uint32_t* argv, uint32_t* envp, int flags) -> uint64_t {
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fextl::vector<const char*> Args;
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fextl::vector<const char*> Envp;
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if (argv) {
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for (int i = 0; argv[i]; i++) {
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Args.push_back(reinterpret_cast<const char*>(static_cast<uintptr_t>(argv[i])));
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}
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Args.push_back(nullptr);
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}
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if (envp) {
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for (int i = 0; envp[i]; i++) {
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Envp.push_back(reinterpret_cast<const char*>(static_cast<uintptr_t>(envp[i])));
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}
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Envp.push_back(nullptr);
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}
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FEX::HLE::ExecveAtArgs AtArgs {
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.dirfd = dirfd,
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.flags = flags,
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};
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auto* const* ArgsPtr = argv ? const_cast<char* const*>(Args.data()) : nullptr;
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auto* const* EnvpPtr = envp ? const_cast<char* const*>(Envp.data()) : nullptr;
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return FEX::HLE::ExecveHandler(Frame, pathname, ArgsPtr, EnvpPtr, AtArgs);
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}));
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REGISTER_SYSCALL_IMPL_X32(wait4, [](FEXCore::Core::CpuStateFrame* Frame, pid_t pid, int* wstatus, int options, struct rusage_32* rusage) -> uint64_t {
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struct rusage usage64 {};
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struct rusage* usage64_p {};
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if (rusage) {
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FaultSafeUserMemAccess::VerifyIsReadable(rusage, sizeof(*rusage));
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usage64 = *rusage;
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usage64_p = &usage64;
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}
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uint64_t Result = ::wait4(pid, wstatus, options, usage64_p);
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if (rusage) {
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FaultSafeUserMemAccess::VerifyIsWritable(rusage, sizeof(*rusage));
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*rusage = usage64;
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}
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SYSCALL_ERRNO();
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});
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REGISTER_SYSCALL_IMPL_X32(waitid,
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[](FEXCore::Core::CpuStateFrame* Frame, int which, pid_t upid, compat_ptr<FEXCore::x86::siginfo_t> info,
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int options, struct rusage_32* rusage) -> uint64_t {
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struct rusage usage64 {};
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struct rusage* usage64_p {};
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siginfo_t info64 {};
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siginfo_t* info64_p {};
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if (rusage) {
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FaultSafeUserMemAccess::VerifyIsReadable(rusage, sizeof(*rusage));
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usage64 = *rusage;
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usage64_p = &usage64;
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}
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if (info) {
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info64_p = &info64;
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}
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uint64_t Result = ::syscall(SYSCALL_DEF(waitid), which, upid, info64_p, options, usage64_p);
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if (Result != -1) {
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if (rusage) {
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FaultSafeUserMemAccess::VerifyIsWritable(rusage, sizeof(*rusage));
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*rusage = usage64;
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}
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if (info) {
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FaultSafeUserMemAccess::VerifyIsWritable(info, sizeof(*info));
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*info = info64;
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}
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}
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SYSCALL_ERRNO();
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});
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}
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} // namespace FEX::HLE::x32
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